OVP Peripheral Model: ArmRtcPL031
Model Specific Information
This page provides introductory usage information for an Imperas OVP peripheral behavioral model.
The page is split into sections providing specific information for this peripheral,
including any ports for connecting into a platform, registers, other component parts, and configuration options and general information for peripheral modeling with Imperas OVP.
Description
ARM PL031 Real Time Clock (RTC)
Reference
ARM PrimeCell Real Time Clock (PL031) Technical Reference Manual (ARM DDI 0224)
Licensing
Open Source Apache 2.0
Location
The RtcPL031 peripheral model is located in an Imperas/OVP installation at the VLNV: arm.ovpworld.org / peripheral / RtcPL031 / 1.0.
Net Ports
This model has the following net ports:
Table : Net Ports
Name | Type | Must Be Connected | Description |
---|
irq | output | F (False) | ARM PL031 RTC |
Bus Slave Ports
This model has the following bus slave ports:
Bus Slave Port: bport1
Table 1: Bus Slave Port: bport1
Name | Size (bytes) | Must Be Connected | Description |
---|
bport1 | 0x1000 | F (False) | |
Table 2: Bus Slave Port: bport1 Registers:
Name | Offset | Width (bits) | Description | R/W | is Volatile |
---|
ab_dr | 0x0 | 32 | Data read | | |
ab_mr | 0x4 | 32 | Match | | |
ab_lr | 0x8 | 32 | Data load | | |
ab_cr | 0xc | 32 | Control | | |
ab_im | 0x10 | 32 | Interrupt mask | | |
ab_is | 0x14 | 32 | Raw interrupt | | |
ab_mis | 0x18 | 32 | Masked interrupt | | |
ab_icr | 0x1c | 32 | Interrupt clear | | |
ab_id0 | 0xfe0 | 32 | | | |
ab_id1 | 0xfe4 | 32 | | | |
ab_id2 | 0xfe8 | 32 | | | |
ab_id3 | 0xfec | 32 | | | |
ab_id4 | 0xff0 | 32 | | | |
ab_id5 | 0xff4 | 32 | | | |
ab_id6 | 0xff8 | 32 | | | |
ab_id7 | 0xffc | 32 | | | |
Platforms that use this peripheral component
Peripheral components can be used in many different platforms, including those developed by Imperas or by other users of OVP. You can use this peripheral in your own platforms.
Table 3: Publicly available platforms using peripheral 'RtcPL031'