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OVP Peripheral Model: ArmSerBusDviRegs

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Model Specific Information

This page provides introductory usage information for an Imperas OVP peripheral behavioral model. The page is split into sections providing specific information for this peripheral, including any ports for connecting into a platform, registers, other component parts, and configuration options and general information for peripheral modeling with Imperas OVP.

Reference

ARM Motherboard Express ATX V2M-P1 Technical Reference Manual(ARM DUI 0447G), Section 4.5.8 Two-wire serial bus interface, SBCon

Limitations

Programmers View, register model only. Does NOT model functionality, just provides registers to allow code to run.

Description

Versatile Express Serial Bus DVI Registers

Licensing

Open Source Apache 2.0

Location

The SerBusDviRegs peripheral model is located in an Imperas/OVP installation at the VLNV: arm.ovpworld.org / peripheral / SerBusDviRegs / 1.0.

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Bus Slave Ports

This model has the following bus slave ports:

Bus Slave Port: bport1

Table : Bus Slave Port: bport1

Table 1: Bus Slave Port: bport1 Registers:

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Platforms that use this peripheral component

Peripheral components can be used in many different platforms, including those developed by Imperas or by other users of OVP. You can use this peripheral in your own platforms.

Table 2: Publicly available platforms using peripheral 'SerBusDviRegs'