OVP Peripheral Model: AtmelAdvancedInterruptController
Model Specific Information
This page provides introductory usage information for an Imperas OVP peripheral behavioral model.
The page is split into sections providing specific information for this peripheral,
including any ports for connecting into a platform, registers, other component parts, and configuration options and general information for peripheral modeling with Imperas OVP.
Licensing
Open Source Apache 2.0
Limitations
This model is sufficient to boot Linux
Description
AIC: Advanced Interrupt Controller This model contains an accurate Register set interface. The functionality has only been implemented to sufficiently boot uClinux The Advanced Interrupt Controller has an 8-level priority, individually maskable, vectored interrupt controller, and drives the NIRQ and NFIQ pins of the ARM7TDMI from: The external fast interrupt line (FIQ) The three external interrupt request lines (IRQ0 - IRQ2) The interrupt signals from the on-chip peripherals The AIC is extensively programmable offering maximum flexibility, and its vectoring features reduce the real-time overhead in handling interrupts. The AIC also features a spurious vector detection feature, which reduces spurious interrupt handling to a minimum, and a protect mode that facilitates the debug capabilities.
Reference
Rev. 1354D ARM08/02
Location
The AdvancedInterruptController peripheral model is located in an Imperas/OVP installation at the VLNV: atmel.ovpworld.org / peripheral / AdvancedInterruptController / 1.0.
Net Ports
This model has the following net ports:
Table : Net Ports
Name | Type | Must Be Connected | Description |
---|
IRQ2 | input | F (False) | |
IRQ1 | input | F (False) | |
IRQ0 | input | F (False) | |
PIOIRQ | input | F (False) | |
WDIRQ | input | F (False) | |
TC2IRQ | input | F (False) | |
TC1IRQ | input | F (False) | |
TC0IRQ | input | F (False) | |
US1IRQ | input | F (False) | |
US0IRQ | input | F (False) | |
SWIRQ | input | F (False) | |
FIQ | input | F (False) | |
NIRQ | output | F (False) | |
NFIQ | output | F (False) | |
Bus Slave Ports
This model has the following bus slave ports:
Bus Slave Port: bp1
Table 1: Bus Slave Port: bp1
Name | Size (bytes) | Must Be Connected | Description |
---|
bp1 | 0x1000 | T (True) | |
Table 2: Bus Slave Port: bp1 Registers:
Name | Offset | Width (bits) | Description | R/W | is Volatile |
---|
REG_AIC_ISCR | 0x12c | 32 | | | |
REG_AIC_ICCR | 0x128 | 32 | | | |
REG_AIC_IDCR | 0x124 | 32 | | | |
REG_AIC_IECR | 0x120 | 32 | | | |
REG_AIC_CISR | 0x114 | 32 | | | |
REG_AIC_IMR | 0x110 | 32 | | | |
REG_AIC_IPR | 0x10c | 32 | | | |
REG_AIC_ISR | 0x108 | 32 | | | |
REG_AIC_FVR | 0x104 | 32 | | | |
REG_AIC_IVR | 0x100 | 32 | | | |
REG_AIC_SVR31 | 0xfc | 32 | | | |
REG_AIC_SVR30 | 0xf8 | 32 | | | |
REG_AIC_SVR29 | 0xf4 | 32 | | | |
REG_AIC_SVR28 | 0xf0 | 32 | | | |
REG_AIC_SVR27 | 0xec | 32 | | | |
REG_AIC_SVR26 | 0xe8 | 32 | | | |
REG_AIC_SVR25 | 0xe4 | 32 | | | |
REG_AIC_SVR24 | 0xe0 | 32 | | | |
REG_AIC_SVR23 | 0xdc | 32 | | | |
REG_AIC_SVR22 | 0xd8 | 32 | | | |
REG_AIC_SVR21 | 0xd4 | 32 | | | |
REG_AIC_SVR20 | 0xd0 | 32 | | | |
REG_AIC_SVR19 | 0xcc | 32 | | | |
REG_AIC_SVR18 | 0xc8 | 32 | | | |
REG_AIC_SVR17 | 0xc4 | 32 | | | |
REG_AIC_SVR16 | 0xc0 | 32 | | | |
REG_AIC_SVR15 | 0xbc | 32 | | | |
REG_AIC_SVR14 | 0xb8 | 32 | | | |
REG_AIC_SVR13 | 0xb4 | 32 | | | |
REG_AIC_SVR12 | 0xb0 | 32 | | | |
REG_AIC_SVR11 | 0xac | 32 | | | |
REG_AIC_SVR10 | 0xa8 | 32 | | | |
REG_AIC_SVR9 | 0xa4 | 32 | | | |
REG_AIC_SVR8 | 0xa0 | 32 | | | |
REG_AIC_SVR7 | 0x9c | 32 | | | |
REG_AIC_SVR6 | 0x98 | 32 | | | |
REG_AIC_SVR5 | 0x94 | 32 | | | |
REG_AIC_SVR4 | 0x90 | 32 | | | |
REG_AIC_SVR3 | 0x8c | 32 | | | |
REG_AIC_SVR2 | 0x88 | 32 | | | |
REG_AIC_SVR1 | 0x84 | 32 | | | |
REG_AIC_SVR0 | 0x80 | 32 | | | |
REG_AIC_SMR31 | 0x7c | 32 | | | |
REG_AIC_SMR30 | 0x78 | 32 | | | |
REG_AIC_SMR29 | 0x74 | 32 | | | |
REG_AIC_SMR28 | 0x70 | 32 | | | |
REG_AIC_SMR27 | 0x6c | 32 | | | |
REG_AIC_SMR26 | 0x68 | 32 | | | |
REG_AIC_SMR25 | 0x64 | 32 | | | |
REG_AIC_SMR24 | 0x60 | 32 | | | |
REG_AIC_SMR23 | 0x5c | 32 | | | |
REG_AIC_SMR22 | 0x58 | 32 | | | |
REG_AIC_SMR21 | 0x54 | 32 | | | |
REG_AIC_SMR20 | 0x50 | 32 | | | |
REG_AIC_SMR19 | 0x4c | 32 | | | |
REG_AIC_SMR18 | 0x48 | 32 | | | |
REG_AIC_SMR17 | 0x44 | 32 | | | |
REG_AIC_SMR16 | 0x40 | 32 | | | |
REG_AIC_SMR15 | 0x3c | 32 | | | |
REG_AIC_SMR14 | 0x38 | 32 | | | |
REG_AIC_SMR13 | 0x34 | 32 | | | |
REG_AIC_SMR12 | 0x30 | 32 | | | |
REG_AIC_SMR11 | 0x2c | 32 | | | |
REG_AIC_SMR10 | 0x28 | 32 | | | |
REG_AIC_SMR9 | 0x24 | 32 | | | |
REG_AIC_SMR8 | 0x20 | 32 | | | |
REG_AIC_SMR7 | 0x1c | 32 | | | |
REG_AIC_SMR6 | 0x18 | 32 | | | |
REG_AIC_SMR5 | 0x14 | 32 | | | |
REG_AIC_SMR4 | 0x10 | 32 | | | |
REG_AIC_SMR3 | 0xc | 32 | | | |
REG_AIC_SMR2 | 0x8 | 32 | | | |
REG_AIC_SMR1 | 0x4 | 32 | | | |
REG_AIC_SMR0 | 0x0 | 32 | | | |
REG_AIC_EOICR | 0x130 | 32 | | | |
REG_AIC_SPU | 0x134 | 32 | | | |
Platforms that use this peripheral component
Peripheral components can be used in many different platforms, including those developed by Imperas or by other users of OVP. You can use this peripheral in your own platforms.
Table 3: Publicly available platforms using peripheral 'AdvancedInterruptController'