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BareMetalArcSingle



OVP Virtual Platform: BareMetalArcSingle

What is a Bare Metal Platform?

A 'Bare Metal' Platform consists of a single processor with memory available over its complete address range.

Bare Metal Platform

This is ideal for execution of a user application that has been compiled for the target processor core using cross-compilation.

Obtaining the BareMetalArcSingle platform and the OVP Simulator

The source and binary of the bare metal platforms are part of the OVP/Imperas downloads and live on a VLNV (Vendor Library Name Version) path.

To download from OVPworld, browse the OVP downloads page and download the OVPsim package. Click here to browse available downloads.

When installed this platform is found in your installation here: ImperasLib/source/arc.ovpworld.org/platform/BareMetalArcSingle/1.0.

Running the Bare Metal Platform

1. Run the installer to install into a local directory on your PC. We recommend you use a path without spaces, for example your home directory.

2. Enter the Demo Directory IMPERAS_HOME/Demo/BareMetalArcSingle

3. On Windows, double-click on the batch file xx.bat and on Linux run the script xx.sh to run a simple application elf file on the Bare Metal Platform.

You will see output something like:
Info (ARM_NEWLIB_RDI_HEAP_INFO) RDI heap_base=0xc0000000 
Hello
Info (ARM_NEWLIB_RDI_EXIT) Process has ended (exit)
Info 
Info ---------------------------------------------------
Info CPU 'CPU1' STATISTICS
Info   Type                  : arm
Info   Nominal MIPS          : 100
Info   Final program counter : 0x91a4
Info   Simulated instructions: 4,175
Info ---------------------------------------------------
Info 
Info ---------------------------------------------------
Info SIMULATION TIME STATISTICS
Info   Simulated time        : 0.00 seconds
Info   User time             : 0.02 seconds
Info   System time           : 0.00 seconds
Info ---------------------------------------------------

Setting Up for Re-building the Application

To rebuild the application and create the elf file you will need 3 things:
  • Cross-Compiler toolchain for thi processor
  • An OVP Installation
  • MSYS / MINGW environment (Windows Users Only)

Download and Installing the Cross-Compiler Toolchain

To download an appropriate tool chain, browse the OVP downloads page and download the package. Click here to browse.
If there is not one available please ask on the forum.

Once downloaded run the installer <packageName>.Windows32.exe for Windows and <packageName>.Linux32.exe for Linux to install on your PC.

Installing MSYS / MINGW Environment (Windows Users Only)

Obtaining and installing the MSYS and MINGW environment is described in Imperas_Installation_and_Getting_Started.pdf.

Rebuilding

You will need to be in the Demo/'baremetaldemodir' directory using an MSYS shell for Windows or a Linux shell.

Re-building the Application
> make application

Re-building the Bare Metal Platform
> make platform

Executing the application on the platform
You can just double click on the .bat file as done previously, or you can run from the msys command line:
> ./BareMetal.OS.exe hello.CROSS.elf



This page provides detailed information about the OVP Virtual Platform Model of the arc.ovpworld.org BareMetalArcSingle platform.

Description

Bare Metal Platform for an ARC Processor. The bare metal platform instantiates a single ARC processor instance. The processor operates using little endian data ordering. It creates contiguous memory from 0x00000000 to 0xFFFFFFFF. The platform can be passed any application compiled to an ARC elf format. ./platform..exe --program application..elf

Licensing

Open Source Apache 2.0

Limitations

BareMetal platform for execution of ARC binary files compiled with FOSS for Synopsys DesignWare ARC Processors CrossCompiler toolchain.

Reference

None, baremetal platform definition

Location

The BareMetalArcSingle virtual platform is located in an Imperas/OVP installation at the VLNV: arc.ovpworld.org / platform / BareMetalArcSingle / 1.0.

Platform Summary

Table : Components in platform

TypeInstanceVendorComponent
Processorcpu1arc.ovpworld.orgarc700
Memorymemoryovpworld.orgram
Busbus(builtin)address width:32

Platform Simulation Attributes

Table 1: Platform Simulation Attributes

AttributeValueDescription
stoponctrlcstoponctrlcStop on control-C



Command Line Control of the Platform

Built-in Arguments

Table 2: Platform Built-in Arguments

AttributeValueDescription
allargsallargsThe Command line parser will accept the complete imperas argument set. Note that this option is ignored in some Imperas products

When running a platform in a Windows or Linux shell several command arguments can be specified. Typically there is a '-help' command which lists the commands available in the platforms.
For example: myplatform.exe -help

Some command line arguments require a value to be provided.
For example: myplatform.exe -program myimagefile.elf

Platform Specific Command Line Arguments

No platform specific command line arguments have been specified.



Processor [arc.ovpworld.org/processor/arc/1.0] instance: cpu1

Processor model type: 'arc' variant '700' definition

Imperas OVP processor models support multiple variants and details of the variants implemented in this model can be found in:
- the Imperas installation located at ImperasLib/source/arc.ovpworld.org/processor/arc/1.0/doc
- the OVP website: OVP_Model_Specific_Information_arc_700.pdf

Description

ARC 700 processor model (ARCv1 architecture)

Licensing

Usage of binary model under license governing simulator usage. Source of model available under Imperas Software License Agreement.

Limitations

Instruction pipelines are not modeled in any way. All instructions are assumed to complete immediately.
Instruction and data caches are not modeled, except for the auxiliary register interface.
External host debug is not modeled, except for the auxiliary register interface.
Real-world timing effects are not modeled. All instructions are assumed to complete in a single cycle.

Verification

Models have been validated correct in a cooperative project between Imperas and ARC

Reference

ARC Processor ARC6xx/ARC7xx Reference Documentation

Debugging

The model has been designed for debug using GNU gdb ARCompact/ARCv2 ISA elf32 version 7.5.1. To ensure correct behavior, enter the following command into gdb before attempting to connect to the processor:
set architecture ARC700
Failure to do this may cause the debugging session to fail because of g-packet size mismatch.

Features

The model implements the full ARCv1 instruction set.
The exact set of core instructions present can be configured by a number of parameters: see information for opt-swap, opt-bitscan, opt-extended-arith and opt-multiply in the table below.
Timer 0 and Timer 1 can be enabled using parameters opt-timer0 and opt-timer1, respectively.
The versions of DCCM and ICCM build config registers can be specified using parameters opt-dccm-version and opt-iccm-version, respectively. The sizes of DCCM, ICCM0 and ICCM1 can be specified using parameters opt-dccm-size, opt-iccm0-size and opt-iccm1-size, respectively. Reset base addresses for the ICCMs can be specified using opt-iccm0-base and opt-iccm1-base. Note that the DCCM reset base address is architecturally defined (0x80000000) and not configurable. When CCMs are present, bus ports called DCCM0, ICCM0 and ICCM1 are created so that CCM contents may be viewed or modified externally by connecting to these ports. Parameter opt-internal-ccms specifies whether CCM memory is modeled internally or externally. If modeled externally, the CCMs must be implemented on a bus which is then connected to the CCM bus ports listed above (this parameter is ignored if CCM ports are unconnected; in that case, CCMs are always modeled internally). Parameter opt-reset-internal-ccms indicates that internally-modeled CCMs should be cleared to zero on a processor reset; if False, then internally-modeled CCMs retain their previous state after a reset.
The set of core registers can be specified using parameter opt-extension-core-regs. This is a 64-bit value in which a 1-bit implies the presence of that core extension register. For example, a value of 0xf00000000ULL implies that extension registers r32-r35 should be configured.
The reset value of the exception vector base register can be specified using parameter opt-intvbase-preset.

Auxiliary Register External Implementation

If parameter "enable-aux-bus" is True, an artifact 36-bit bus "Auxiliary" is enabled. Slave callbacks installed on this bus can be used to implement auxiliary register behavior (use opBusSlaveNew or icmMapExternalMemory, depending on the client API). An auxiliary with 32-bit index 0xABCDEFGH is mapped on the bus at address 0xABCDEFGH0.

Instance Parameters

Several parameters can be specified when a processor is instanced in a platform. For this processor instance 'cpu1' it has been instanced with the following parameters:

Table 3: Processor Instance 'cpu1' Parameters (Configurations)

ParameterValueDescription
mips100The nominal MIPS for the processor
semihostvendorarc.ovpworld.orgThe VLNV vendor name of a Semihost library
semihostnamearcNewlibThe VLNV name of a Semihost library

Table 4: Processor Instance 'cpu1' Parameters (Attributes)

Parameter NameValueType
variant700enum

Memory Map for processor 'cpu1' bus: 'bus'

Processor instance 'cpu1' is connected to bus 'bus' using master port 'INSTRUCTION'.

Processor instance 'cpu1' is connected to bus 'bus' using master port 'DATA'.

Table 5: Memory Map ( 'cpu1' / 'bus' [width: 32] )

Lo AddressHi AddressInstanceComponent
0x00xFFFFFFFFmemoryram

Net Connections to processor: 'cpu1'

There are no nets connected to this processor.


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