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OVP Peripheral Model: CadenceUart

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Model Specific Information

This page provides introductory usage information for an Imperas OVP peripheral behavioral model. The page is split into sections providing specific information for this peripheral, including any ports for connecting into a platform, registers, other component parts, and configuration options and general information for peripheral modeling with Imperas OVP.

Limitations

There is no modeling of physical aspects of the UART, such as baud rates etc.

It has basic functionality to support Linux boot on the Xilinx Zync platform.

This is an incomplete model of the Cadence UART (uartps) as used on the Xilinx Zync devices.

Description

Cadence UART (Xilinx Zync Platform)

Licensing

Open Source Apache 2.0

Reference

Zynq-7000 TRM (https://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf)

Location

The uart peripheral model is located in an Imperas/OVP installation at the VLNV: cadence.ovpworld.org / peripheral / uart / 1.0.

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Peripheral Instance Parameters

This model accepts the following parameters:

Table : Peripheral Parameters

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Net Ports

This model has the following net ports:

Table 1: Net Ports

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Bus Slave Ports

This model has the following bus slave ports:

Bus Slave Port: bport1

Table 2: Bus Slave Port: bport1

Table 3: Bus Slave Port: bport1 Registers:

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Platforms that use this peripheral component

Peripheral components can be used in many different platforms, including those developed by Imperas or by other users of OVP. You can use this peripheral in your own platforms.

Table 4: Publicly available platforms using peripheral 'uart'