OVP Peripheral Model: CadenceUart
Model Specific Information
This page provides introductory usage information for an Imperas OVP peripheral behavioral model.
The page is split into sections providing specific information for this peripheral,
including any ports for connecting into a platform, registers, other component parts, and configuration options and general information for peripheral modeling with Imperas OVP.
Limitations
There is no modeling of physical aspects of the UART, such as baud rates etc.
It has basic functionality to support Linux boot on the Xilinx Zync platform.
This is an incomplete model of the Cadence UART (uartps) as used on the Xilinx Zync devices.
Description
Cadence UART (Xilinx Zync Platform)
Licensing
Open Source Apache 2.0
Reference
Zynq-7000 TRM (https://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf)
Location
The uart peripheral model is located in an Imperas/OVP installation at the VLNV: cadence.ovpworld.org / peripheral / uart / 1.0.
Peripheral Instance Parameters
This model accepts the following parameters:
Table : Peripheral Parameters
Name | Type | Description |
---|
xchars | uns32 | Width of console in characters |
connectnonblocking | bool | If set, simulation can begin before the connection is made |
finishOnDisconnect | bool | If set, disconnecting the port will cause the simulation to finish |
log | bool | If specified, serial output will go to simulator log |
portFile | string | If portnum was specified as zero, write the port number to this file when it's known |
outfile | string | Name of file to write device output |
infile | string | Name of file to use for device source |
portnum | uns32 | If set, listen on this port. If set to zero, allocate a port from the pool and listen on that. |
console | bool | If specified, port number is ignored, and a console pops up automatically |
charmode | bool | |
ychars | uns32 | Height of console in characters |
record | string | Record external events into this file |
replay | string | Replay external events from this file |
Net Ports
This model has the following net ports:
Table 1: Net Ports
Name | Type | Must Be Connected | Description |
---|
irq | output | F (False) | |
Bus Slave Ports
This model has the following bus slave ports:
Bus Slave Port: bport1
Table 2: Bus Slave Port: bport1
Name | Size (bytes) | Must Be Connected | Description |
---|
bport1 | 0x1000 | T (True) | |
Table 3: Bus Slave Port: bport1 Registers:
Name | Offset | Width (bits) | Description | R/W | is Volatile |
---|
ab_TX_RX_FIFO | 0x30 | 32 | Transmit and Receive FIFO | | |
ab_Channel_sts | 0x2c | 32 | Channel Status Register | | |
ab_Modem_sts | 0x28 | 32 | Modem Status Register (no effect) | | |
ab_Modem_ctrl | 0x24 | 32 | Modem Control Register (no effect) | | |
ab_Rcvr_FIFO_trigger_level | 0x20 | 32 | Receiver FIFO Trigger Level Register | | |
ab_Rcvr_timeout | 0x1c | 32 | Receiver Timeout Register (no effect) | | |
ab_Baud_rate_gen | 0x18 | 32 | Baud Rate Generator Register (no effect) | | |
ab_Chnl_int_sts | 0x14 | 32 | Channel Interrupt Status Register | | |
ab_Intrpt_mask | 0x10 | 32 | Interrupt Mask Register | | |
ab_Intrpt_dis | 0xc | 32 | Interrupt Disable Register | | |
ab_Intrpt_en | 0x8 | 32 | Interrupt Enable Register | | |
ab_mode | 0x4 | 32 | UART Mode Register (no effect) | | |
ab_Control | 0x0 | 32 | UART Control Register | | |
ab_Baud_rate_divider | 0x34 | 32 | Baud Rate Divider Register (no effect) | | |
ab_Flow_delay | 0x38 | 32 | Flow Control Delay Register (no effect) | | |
ab_Tx_FIFO_trigger_level | 0x44 | 32 | Transmitter FIFO Trigger Level Register (no effect) | | |
Platforms that use this peripheral component
Peripheral components can be used in many different platforms, including those developed by Imperas or by other users of OVP. You can use this peripheral in your own platforms.
Table 4: Publicly available platforms using peripheral 'uart'