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CadenceUart



OVP Peripheral Model: CadenceUart



Model Specific Information

This page provides introductory usage information for an Imperas OVP peripheral behavioral model. The page is split into sections providing specific information for this peripheral, including any ports for connecting into a platform, registers, other component parts, and configuration options and general information for peripheral modeling with Imperas OVP.

Limitations

There is no modeling of physical aspects of the UART, such as baud rates etc.

It has basic functionality to support Linux boot on the Xilinx Zync platform.

This is an incomplete model of the Cadence UART (uartps) as used on the Xilinx Zync devices.

Description

Cadence UART (Xilinx Zync Platform)

Licensing

Open Source Apache 2.0

Reference

Zynq-7000 TRM (https://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf)

Location

The uart peripheral model is located in an Imperas/OVP installation at the VLNV: cadence.ovpworld.org / peripheral / uart / 1.0.



Peripheral Instance Parameters

This model accepts the following parameters:

Table : Peripheral Parameters

NameTypeDescription
xcharsuns32Width of console in characters
connectnonblockingboolIf set, simulation can begin before the connection is made
finishOnDisconnectboolIf set, disconnecting the port will cause the simulation to finish
logboolIf specified, serial output will go to simulator log
portFilestringIf portnum was specified as zero, write the port number to this file when it's known
outfilestringName of file to write device output
infilestringName of file to use for device source
portnumuns32If set, listen on this port. If set to zero, allocate a port from the pool and listen on that.
consoleboolIf specified, port number is ignored, and a console pops up automatically
charmodebool
ycharsuns32Height of console in characters
recordstringRecord external events into this file
replaystringReplay external events from this file



Net Ports

This model has the following net ports:

Table 1: Net Ports

NameTypeMust Be ConnectedDescription
irqoutputF (False)



Bus Slave Ports

This model has the following bus slave ports:

Bus Slave Port: bport1

Table 2: Bus Slave Port: bport1

NameSize (bytes)Must Be ConnectedDescription
bport10x1000T (True)

Table 3: Bus Slave Port: bport1 Registers:

NameOffsetWidth (bits)DescriptionR/Wis Volatile
ab_TX_RX_FIFO0x3032Transmit and Receive FIFO
ab_Channel_sts0x2c32Channel Status Register
ab_Modem_sts0x2832Modem Status Register (no effect)
ab_Modem_ctrl0x2432Modem Control Register (no effect)
ab_Rcvr_FIFO_trigger_level0x2032Receiver FIFO Trigger Level Register
ab_Rcvr_timeout0x1c32Receiver Timeout Register (no effect)
ab_Baud_rate_gen0x1832Baud Rate Generator Register (no effect)
ab_Chnl_int_sts0x1432Channel Interrupt Status Register
ab_Intrpt_mask0x1032Interrupt Mask Register
ab_Intrpt_dis0xc32Interrupt Disable Register
ab_Intrpt_en0x832Interrupt Enable Register
ab_mode0x432UART Mode Register (no effect)
ab_Control0x032UART Control Register
ab_Baud_rate_divider0x3432Baud Rate Divider Register (no effect)
ab_Flow_delay0x3832Flow Control Delay Register (no effect)
ab_Tx_FIFO_trigger_level0x4432Transmitter FIFO Trigger Level Register (no effect)



Platforms that use this peripheral component

Peripheral components can be used in many different platforms, including those developed by Imperas or by other users of OVP. You can use this peripheral in your own platforms.

Table 4: Publicly available platforms using peripheral 'uart'

Platform NameVendor
Zynq_PSxilinx.ovpworld.org



CadencePeripherals
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