OVP Peripheral Model: FreescaleKinetisADC
Model Specific Information
This page provides introductory usage information for an Imperas OVP peripheral behavioral model.
The page is split into sections providing specific information for this peripheral,
including any ports for connecting into a platform, registers, other component parts, and configuration options and general information for peripheral modeling with Imperas OVP.
Limitations
Provides the base behaviour for the OVP Freescale Kinetis platforms
Description
Model of the ADC peripheral used on the Freescale Kinetis platform
Reference
www.freescale.com/Kinetis
Licensing
Open Source Apache 2.0
Location
The KinetisADC peripheral model is located in an Imperas/OVP installation at the VLNV: freescale.ovpworld.org / peripheral / KinetisADC / 1.0.
Peripheral Instance Parameters
This model accepts the following parameters:
Table : Peripheral Parameters
Name | Type | Description |
---|
input_vrefl | uns32 | |
input_vrefh | uns32 | |
configure_sc3 | uns32 | |
configure_sc2 | uns32 | |
configure_cv2 | uns32 | |
configure_cv1 | uns32 | |
configure_cfg2 | uns32 | |
configure_cfg1 | uns32 | |
configure_sc1b | uns32 | |
configure_sc1a | uns32 | |
bus_clock_freq | uns32 | |
stimFile0 | string | |
Net Ports
This model has the following net ports:
Table 1: Net Ports
Name | Type | Must Be Connected | Description |
---|
DmaReq | output | F (False) | |
Interrupt | output | F (False) | |
AdInId | output | F (False) | |
Vrefsl | input | F (False) | |
Vrefsh | input | F (False) | |
AdIn | input | F (False) | |
HwTrig | input | F (False) | |
AltClk | input | F (False) | |
Reset | input | F (False) | |
Bus Slave Ports
This model has the following bus slave ports:
Bus Slave Port: bport1
Table 2: Bus Slave Port: bport1
Name | Size (bytes) | Must Be Connected | Description |
---|
bport1 | 0x1000 | F (False) | |
Table 3: Bus Slave Port: bport1 Registers:
Name | Offset | Width (bits) | Description | R/W | is Volatile |
---|
ab_CLMS | 0x58 | 32 | ADC minus-side general calibration value register, offset: 0x58 | | |
ab_CLMD | 0x54 | 32 | ADC minus-side general calibration value register, offset: 0x54 | | |
ab_PGA | 0x50 | 32 | ADC PGA register, offset: 0x50 | | |
ab_CLP0 | 0x4c | 32 | ADC plus-side general calibration value register, offset: 0x4C | | |
ab_CLP1 | 0x48 | 32 | ADC plus-side general calibration value register, offset: 0x48 | | |
ab_CLP2 | 0x44 | 32 | ADC plus-side general calibration value register, offset: 0x44 | | |
ab_CLP3 | 0x40 | 32 | ADC plus-side general calibration value register, offset: 0x40 | | |
ab_CLP4 | 0x3c | 32 | ADC plus-side general calibration value register, offset: 0x3C | | |
ab_CLPS | 0x38 | 32 | ADC plus-side general calibration value register, offset: 0x38 | | |
ab_CLPD | 0x34 | 32 | ADC plus-side general calibration value register, offset: 0x34 | | |
ab_MG | 0x30 | 32 | ADC minus-side gain register, offset: 0x30 | | |
ab_PG | 0x2c | 32 | ADC plus-side gain register, offset: 0x2C | | |
ab_OFS | 0x28 | 32 | ADC offset correction register, offset: 0x28 | | |
ab_SC3 | 0x24 | 32 | Status and control register 3, offset: 0x24 | | |
ab_SC2 | 0x20 | 32 | Status and control register 2, offset: 0x20 | | |
ab_CV2 | 0x1c | 32 | Compare value registers, offset: 0x1C | | |
ab_CV1 | 0x18 | 32 | Compare value registers, offset: 0x18 | | |
ab_RB | 0x14 | 32 | ADC data result register, array offset: 0x10, array step: 0x4 | | |
ab_RA | 0x10 | 32 | ADC data result register, array offset: 0x10, array step: 0x4 | | |
ab_CFG2 | 0xc | 32 | Configuration register 2, offset: 0xC | | |
ab_CFG1 | 0x8 | 32 | ADC configuration register 1, offset: 0x8 | | |
ab_SC1B | 0x4 | 32 | ADC status and control registers 1, array offset: 0x0, array step: 0x4 | | |
ab_SC1A | 0x0 | 32 | ADC status and control registers 1, array offset: 0x0, array step: 0x4 | | |
ab_CLM4 | 0x5c | 32 | ADC minus-side general calibration value register, offset: 0x5C | | |
ab_CLM3 | 0x60 | 32 | ADC minus-side general calibration value register, offset: 0x60 | | |
ab_CLM2 | 0x64 | 32 | ADC minus-side general calibration value register, offset: 0x64 | | |
ab_CLM1 | 0x68 | 32 | ADC minus-side general calibration value register, offset: 0x68 | | |
ab_CLM0 | 0x6c | 32 | ADC minus-side general calibration value register, offset: 0x6C | | |
Platforms that use this peripheral component
Peripheral components can be used in many different platforms, including those developed by Imperas or by other users of OVP. You can use this peripheral in your own platforms.
Table 4: Publicly available platforms using peripheral 'KinetisADC'