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FreescaleKinetisDMA



OVP Peripheral Model: FreescaleKinetisDMA



Model Specific Information

This page provides introductory usage information for an Imperas OVP peripheral behavioral model. The page is split into sections providing specific information for this peripheral, including any ports for connecting into a platform, registers, other component parts, and configuration options and general information for peripheral modeling with Imperas OVP.

Description

Model of the DMA peripheral used on the Freescale Kinetis platform

Limitations

Provides the base behaviour for the OVP Freescale Kinetis platforms

Reference

www.freescale.com/Kinetis

Licensing

Open Source Apache 2.0

Location

The KinetisDMA peripheral model is located in an Imperas/OVP installation at the VLNV: freescale.ovpworld.org / peripheral / KinetisDMA / 1.0.



Net Ports

This model has the following net ports:

Table : Net Ports

NameTypeMust Be ConnectedDescription
ResetinputF (False)
eDMARequestinputF (False)
eDMADoneoutputF (False)
errorInterruptoutputF (False)DMA Error Interrupt port
dmaInterrupt_ch0outputF (False)DMA Done Interrupt
dmaInterrupt_ch1outputF (False)DMA Done Interrupt
dmaInterrupt_ch2outputF (False)DMA Done Interrupt
dmaInterrupt_ch3outputF (False)DMA Done Interrupt
dmaInterrupt_ch4outputF (False)DMA Done Interrupt
dmaInterrupt_ch5outputF (False)DMA Done Interrupt
dmaInterrupt_ch6outputF (False)DMA Done Interrupt
dmaInterrupt_ch7outputF (False)DMA Done Interrupt
dmaInterrupt_ch8outputF (False)DMA Done Interrupt
dmaInterrupt_ch9outputF (False)DMA Done Interrupt
dmaInterrupt_ch10outputF (False)DMA Done Interrupt
dmaInterrupt_ch11outputF (False)DMA Done Interrupt
dmaInterrupt_ch12outputF (False)DMA Done Interrupt
dmaInterrupt_ch13outputF (False)DMA Done Interrupt
dmaInterrupt_ch14outputF (False)DMA Done Interrupt
dmaInterrupt_ch15outputF (False)DMA Done Interrupt
dmaInterrupt_ch16outputF (False)DMA Done Interrupt
dmaInterrupt_ch17outputF (False)DMA Done Interrupt
dmaInterrupt_ch18outputF (False)DMA Done Interrupt
dmaInterrupt_ch19outputF (False)DMA Done Interrupt
dmaInterrupt_ch20outputF (False)DMA Done Interrupt
dmaInterrupt_ch21outputF (False)DMA Done Interrupt
dmaInterrupt_ch22outputF (False)DMA Done Interrupt
dmaInterrupt_ch23outputF (False)DMA Done Interrupt
dmaInterrupt_ch24outputF (False)DMA Done Interrupt
dmaInterrupt_ch25outputF (False)DMA Done Interrupt
dmaInterrupt_ch26outputF (False)DMA Done Interrupt
dmaInterrupt_ch27outputF (False)DMA Done Interrupt
dmaInterrupt_ch28outputF (False)DMA Done Interrupt
dmaInterrupt_ch29outputF (False)DMA Done Interrupt
dmaInterrupt_ch30outputF (False)DMA Done Interrupt
dmaInterrupt_ch31outputF (False)DMA Done Interrupt



Bus Master Ports

This model has the following bus master ports:

Bus Master Port: MREAD

Table 1: MREAD

NameAddress Width (bits)Description
MREAD32DMA Master Read of address space

Bus Master Port: MWRITE

Table 2: MWRITE

NameAddress Width (bits)Description
MWRITE32DMA Master Write of address space



Bus Slave Ports

This model has the following bus slave ports:

Bus Slave Port: bport1

Table 3: Bus Slave Port: bport1

NameSize (bytes)Must Be ConnectedDescription
bport10x2000F (False)

Table 4: Bus Slave Port: bport1 Registers:

NameOffsetWidth (bits)DescriptionR/Wis Volatile
ab_CR0x032Control Register, offset: 0x0
ab_ES0x432Error Status Register, offset: 0x4
ab_ERQ0xc32Enable Request Register, offset: 0xC
ab_EEI0x1432
ab_CS_EEI_ERC0x1832Clear/Set EEI, ERC
ab_DNE_SRT_ERR_INT0x1c32Clear/Set DNE, START, ERR, INT registers
ab_INT0x2432
ab_ERR0x2c32Error Register, offset: 0x2C
ab_HRS0x3432
ab_DCHPRI3_00x10032Channel n Priority Registers 3 to 0
ab_DCHPRI7_40x10432
ab_DCHPRI11_80x10832
ab_DCHPRI15_120x10c32
ab_DCHPRI19_160x11032
ab_DCHPRI23_200x11432
ab_DCHPRI27_240x11832
ab_DCHPRI31_280x11c32
TCD0_SADDR0x100032TCD Source Address
TCD0_SOFF_ATTR0x100432TCD Signed Source Address Offset
TCD0_NBYTES0x100832TCD Signed Minor Loop Offset, Minor Loop Disabled
TCD0_SLAST0x100c32
TCD0_DADDR0x101032
TCD0_DOFF_CITER0x101432
TCD0_DLASTSGA0x101832
TCD0_CSR_BITER0x101c32
TCD1_SADDR0x102032TCD Source Address
TCD1_SOFF_ATTR0x102432TCD Signed Source Address Offset
TCD1_NBYTES0x102832TCD Signed Minor Loop Offset, Minor Loop Disabled
TCD1_SLAST0x102c32
TCD1_DADDR0x103032
TCD1_DOFF_CITER0x103432
TCD1_DLASTSGA0x103832
TCD1_CSR_BITER0x103c32
TCD2_SADDR0x104032TCD Source Address
TCD2_SOFF_ATTR0x104432TCD Signed Source Address Offset
TCD2_NBYTES0x104832TCD Signed Minor Loop Offset, Minor Loop Disabled
TCD2_SLAST0x104c32
TCD2_DADDR0x105032
TCD2_DOFF_CITER0x105432
TCD2_DLASTSGA0x105832
TCD2_CSR_BITER0x105c32
TCD3_SADDR0x106032TCD Source Address
TCD3_SOFF_ATTR0x106432TCD Signed Source Address Offset
TCD3_NBYTES0x106832TCD Signed Minor Loop Offset, Minor Loop Disabled
TCD3_SLAST0x106c32
TCD3_DADDR0x107032
TCD3_DOFF_CITER0x107432
TCD3_DLASTSGA0x107832
TCD3_CSR_BITER0x107c32
TCD4_SADDR0x108032TCD Source Address
TCD4_SOFF_ATTR0x108432TCD Signed Source Address Offset
TCD4_NBYTES0x108832TCD Signed Minor Loop Offset, Minor Loop Disabled
TCD4_SLAST0x108c32
TCD4_DADDR0x109032
TCD4_DOFF_CITER0x109432
TCD4_DLASTSGA0x109832
TCD4_CSR_BITER0x109c32
TCD5_SADDR0x10a032TCD Source Address
TCD5_SOFF_ATTR0x10a432TCD Signed Source Address Offset
TCD5_NBYTES0x10a832TCD Signed Minor Loop Offset, Minor Loop Disabled
TCD5_SLAST0x10ac32
TCD5_DADDR0x10b032
TCD5_DOFF_CITER0x10b432
TCD5_DLASTSGA0x10b832
TCD5_CSR_BITER0x10bc32
TCD6_SADDR0x10c032TCD Source Address
TCD6_SOFF_ATTR0x10c432TCD Signed Source Address Offset
TCD6_NBYTES0x10c832TCD Signed Minor Loop Offset, Minor Loop Disabled
TCD6_SLAST0x10cc32
TCD6_DADDR0x10d032
TCD6_DOFF_CITER0x10d432
TCD6_DLASTSGA0x10d832
TCD6_CSR_BITER0x10dc32
TCD7_SADDR0x10e032TCD Source Address
TCD7_SOFF_ATTR0x10e432TCD Signed Source Address Offset
TCD7_NBYTES0x10e832TCD Signed Minor Loop Offset, Minor Loop Disabled
TCD7_SLAST0x10ec32
TCD7_DADDR0x10f032
TCD7_DOFF_CITER0x10f432
TCD7_DLASTSGA0x10f832
TCD7_CSR_BITER0x10fc32
TCD8_SADDR0x110032TCD Source Address
TCD8_SOFF_ATTR0x110432TCD Signed Source Address Offset
TCD8_NBYTES0x110832TCD Signed Minor Loop Offset, Minor Loop Disabled
TCD8_SLAST0x110c32
TCD8_DADDR0x111032
TCD8_DOFF_CITER0x111432
TCD8_DLASTSGA0x111832
TCD8_CSR_BITER0x111c32
TCD9_SADDR0x112032TCD Source Address
TCD9_SOFF_ATTR0x112432TCD Signed Source Address Offset
TCD9_NBYTES0x112832TCD Signed Minor Loop Offset, Minor Loop Disabled
TCD9_SLAST0x112c32
TCD9_DADDR0x113032
TCD9_DOFF_CITER0x113432
TCD9_DLASTSGA0x113832
TCD9_CSR_BITER0x113c32
TCD10_SADDR0x114032TCD Source Address
TCD10_SOFF_ATTR0x114432TCD Signed Source Address Offset
TCD10_NBYTES0x114832TCD Signed Minor Loop Offset, Minor Loop Disabled
TCD10_SLAST0x114c32
TCD10_DADDR0x115032
TCD10_DOFF_CITER0x115432
TCD10_DLASTSGA0x115832
TCD10_CSR_BITER0x115c32
TCD11_SADDR0x116032TCD Source Address
TCD11_SOFF_ATTR0x116432TCD Signed Source Address Offset
TCD11_NBYTES0x116832TCD Signed Minor Loop Offset, Minor Loop Disabled
TCD11_SLAST0x116c32
TCD11_DADDR0x117032
TCD11_DOFF_CITER0x117432
TCD11_DLASTSGA0x117832
TCD11_CSR_BITER0x117c32
TCD12_SADDR0x118032TCD Source Address
TCD12_SOFF_ATTR0x118432TCD Signed Source Address Offset
TCD12_NBYTES0x118832TCD Signed Minor Loop Offset, Minor Loop Disabled
TCD12_SLAST0x118c32
TCD12_DADDR0x119032
TCD12_DOFF_CITER0x119432
TCD12_DLASTSGA0x119832
TCD12_CSR_BITER0x119c32
TCD13_SADDR0x11a032TCD Source Address
TCD13_SOFF_ATTR0x11a432TCD Signed Source Address Offset
TCD13_NBYTES0x11a832TCD Signed Minor Loop Offset, Minor Loop Disabled
TCD13_SLAST0x11ac32
TCD13_DADDR0x11b032
TCD13_DOFF_CITER0x11b432
TCD13_DLASTSGA0x11b832
TCD13_CSR_BITER0x11bc32
TCD14_SADDR0x11c032TCD Source Address
TCD14_SOFF_ATTR0x11c432TCD Signed Source Address Offset
TCD14_NBYTES0x11c832TCD Signed Minor Loop Offset, Minor Loop Disabled
TCD14_SLAST0x11cc32
TCD14_DADDR0x11d032
TCD14_DOFF_CITER0x11d432
TCD14_DLASTSGA0x11d832
TCD14_CSR_BITER0x11dc32
TCD15_SADDR0x11e032TCD Source Address
TCD15_SOFF_ATTR0x11e432TCD Signed Source Address Offset
TCD15_NBYTES0x11e832TCD Signed Minor Loop Offset, Minor Loop Disabled
TCD15_SLAST0x11ec32
TCD15_DADDR0x11f032
TCD15_DOFF_CITER0x11f432
TCD15_DLASTSGA0x11f832
TCD15_CSR_BITER0x11fc32
TCD16_SADDR0x120032TCD Source Address
TCD16_SOFF_ATTR0x120432TCD Signed Source Address Offset
TCD16_NBYTES0x120832TCD Signed Minor Loop Offset, Minor Loop Disabled
TCD16_SLAST0x120c32
TCD16_DADDR0x121032
TCD16_DOFF_CITER0x121432
TCD16_DLASTSGA0x121832
TCD16_CSR_BITER0x121c32
TCD17_SADDR0x122032TCD Source Address
TCD17_SOFF_ATTR0x122432TCD Signed Source Address Offset
TCD17_NBYTES0x122832TCD Signed Minor Loop Offset, Minor Loop Disabled
TCD17_SLAST0x122c32
TCD17_DADDR0x123032
TCD17_DOFF_CITER0x123432
TCD17_DLASTSGA0x123832
TCD17_CSR_BITER0x123c32
TCD18_SADDR0x124032TCD Source Address
TCD18_SOFF_ATTR0x124432TCD Signed Source Address Offset
TCD18_NBYTES0x124832TCD Signed Minor Loop Offset, Minor Loop Disabled
TCD18_SLAST0x124c32
TCD18_DADDR0x125032
TCD18_DOFF_CITER0x125432
TCD18_DLASTSGA0x125832
TCD18_CSR_BITER0x125c32
TCD19_SADDR0x126032TCD Source Address
TCD19_SOFF_ATTR0x126432TCD Signed Source Address Offset
TCD19_NBYTES0x126832TCD Signed Minor Loop Offset, Minor Loop Disabled
TCD19_SLAST0x126c32
TCD19_DADDR0x127032
TCD19_DOFF_CITER0x127432
TCD19_DLASTSGA0x127832
TCD19_CSR_BITER0x127c32
TCD20_SADDR0x128032TCD Source Address
TCD20_SOFF_ATTR0x128432TCD Signed Source Address Offset
TCD20_NBYTES0x128832TCD Signed Minor Loop Offset, Minor Loop Disabled
TCD20_SLAST0x128c32
TCD20_DADDR0x129032
TCD20_DOFF_CITER0x129432
TCD20_DLASTSGA0x129832
TCD20_CSR_BITER0x129c32
TCD21_SADDR0x12a032TCD Source Address
TCD21_SOFF_ATTR0x12a432TCD Signed Source Address Offset
TCD21_NBYTES0x12a832TCD Signed Minor Loop Offset, Minor Loop Disabled
TCD21_SLAST0x12ac32
TCD21_DADDR0x12b032
TCD21_DOFF_CITER0x12b432
TCD21_DLASTSGA0x12b832
TCD21_CSR_BITER0x12bc32
TCD22_SADDR0x12c032TCD Source Address
TCD22_SOFF_ATTR0x12c432TCD Signed Source Address Offset
TCD22_NBYTES0x12c832TCD Signed Minor Loop Offset, Minor Loop Disabled
TCD22_SLAST0x12cc32
TCD22_DADDR0x12d032
TCD22_DOFF_CITER0x12d432
TCD22_DLASTSGA0x12d832
TCD22_CSR_BITER0x12dc32
TCD23_SADDR0x12e032TCD Source Address
TCD23_SOFF_ATTR0x12e432TCD Signed Source Address Offset
TCD23_NBYTES0x12e832TCD Signed Minor Loop Offset, Minor Loop Disabled
TCD23_SLAST0x12ec32
TCD23_DADDR0x12f032
TCD23_DOFF_CITER0x12f432
TCD23_DLASTSGA0x12f832
TCD23_CSR_BITER0x12fc32
TCD24_SADDR0x130032TCD Source Address
TCD24_SOFF_ATTR0x130432TCD Signed Source Address Offset
TCD24_NBYTES0x130832TCD Signed Minor Loop Offset, Minor Loop Disabled
TCD24_SLAST0x130c32
TCD24_DADDR0x131032
TCD24_DOFF_CITER0x131432
TCD24_DLASTSGA0x131832
TCD24_CSR_BITER0x131c32
TCD25_SADDR0x132032TCD Source Address
TCD25_SOFF_ATTR0x132432TCD Signed Source Address Offset
TCD25_NBYTES0x132832TCD Signed Minor Loop Offset, Minor Loop Disabled
TCD25_SLAST0x132c32
TCD25_DADDR0x133032
TCD25_DOFF_CITER0x133432
TCD25_DLASTSGA0x133832
TCD25_CSR_BITER0x133c32
TCD26_SADDR0x134032TCD Source Address
TCD26_SOFF_ATTR0x134432TCD Signed Source Address Offset
TCD26_NBYTES0x134832TCD Signed Minor Loop Offset, Minor Loop Disabled
TCD26_SLAST0x134c32
TCD26_DADDR0x135032
TCD26_DOFF_CITER0x135432
TCD26_DLASTSGA0x135832
TCD26_CSR_BITER0x135c32
TCD27_SADDR0x136032TCD Source Address
TCD27_SOFF_ATTR0x136432TCD Signed Source Address Offset
TCD27_NBYTES0x136832TCD Signed Minor Loop Offset, Minor Loop Disabled
TCD27_SLAST0x136c32
TCD27_DADDR0x137032
TCD27_DOFF_CITER0x137432
TCD27_DLASTSGA0x137832
TCD27_CSR_BITER0x137c32
TCD28_SADDR0x138032TCD Source Address
TCD28_SOFF_ATTR0x138432TCD Signed Source Address Offset
TCD28_NBYTES0x138832TCD Signed Minor Loop Offset, Minor Loop Disabled
TCD28_SLAST0x138c32
TCD28_DADDR0x139032
TCD28_DOFF_CITER0x139432
TCD28_DLASTSGA0x139832
TCD28_CSR_BITER0x139c32
TCD29_SADDR0x13a032TCD Source Address
TCD29_SOFF_ATTR0x13a432TCD Signed Source Address Offset
TCD29_NBYTES0x13a832TCD Signed Minor Loop Offset, Minor Loop Disabled
TCD29_SLAST0x13ac32
TCD29_DADDR0x13b032
TCD29_DOFF_CITER0x13b432
TCD29_DLASTSGA0x13b832
TCD29_CSR_BITER0x13bc32
TCD30_SADDR0x13c032TCD Source Address
TCD30_SOFF_ATTR0x13c432TCD Signed Source Address Offset
TCD30_NBYTES0x13c832TCD Signed Minor Loop Offset, Minor Loop Disabled
TCD30_SLAST0x13cc32
TCD30_DADDR0x13d032
TCD30_DOFF_CITER0x13d432
TCD30_DLASTSGA0x13d832
TCD30_CSR_BITER0x13dc32
TCD31_SADDR0x13e032TCD Source Address
TCD31_SOFF_ATTR0x13e432TCD Signed Source Address Offset
TCD31_NBYTES0x13e832TCD Signed Minor Loop Offset, Minor Loop Disabled
TCD31_SLAST0x13ec32
TCD31_DADDR0x13f032
TCD31_DOFF_CITER0x13f432
TCD31_DLASTSGA0x13f832
TCD31_CSR_BITER0x13fc32



Platforms that use this peripheral component

Peripheral components can be used in many different platforms, including those developed by Imperas or by other users of OVP. You can use this peripheral in your own platforms.

Table 5: Publicly available platforms using peripheral 'KinetisDMA'

Platform NameVendor
FreescaleKinetis60freescale.ovpworld.org
FreescaleKinetis64freescale.ovpworld.org



FreescalePeripherals
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