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OVP Peripheral Model: FreescaleKinetisMCG

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Model Specific Information

This page provides introductory usage information for an Imperas OVP peripheral behavioral model. The page is split into sections providing specific information for this peripheral, including any ports for connecting into a platform, registers, other component parts, and configuration options and general information for peripheral modeling with Imperas OVP.

Description

Freescale Multipurpose Clock Generator

Limitations

Only models status register reads, based on writes to configuration registers atc register ATME bit is modeled as RAZ/WI

Licensing

Open Source Apache 2.0

Reference

Freescale Kinetis MCG

Location

The KinetisMCG peripheral model is located in an Imperas/OVP installation at the VLNV: freescale.ovpworld.org / peripheral / KinetisMCG / 1.0.

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Net Ports

This model has the following net ports:

Table : Net Ports

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Bus Slave Ports

This model has the following bus slave ports:

Bus Slave Port: bport1

Table 1: Bus Slave Port: bport1

Table 2: Bus Slave Port: bport1 Registers:

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Platforms that use this peripheral component

Peripheral components can be used in many different platforms, including those developed by Imperas or by other users of OVP. You can use this peripheral in your own platforms.

Table 3: Publicly available platforms using peripheral 'KinetisMCG'