OVP Peripheral Model: FreescaleKinetisSIM

Model Specific Information

This page provides introductory usage information for an Imperas OVP peripheral behavioral model. The page is split into sections providing specific information for this peripheral, including any ports for connecting into a platform, registers, other component parts, and configuration options and general information for peripheral modeling with Imperas OVP.


Model of the SIM peripheral used on the Freescale Kinetis platform


Provides the base behaviour for the OVP Freescale Kinetis platforms



Open Source Apache 2.0


The KinetisSIM peripheral model is located in an Imperas/OVP installation at the VLNV: / peripheral / KinetisSIM / 1.0.

Net Ports

This model has the following net ports:

Table : Net Ports

NameTypeMust Be ConnectedDescription
ResetinputF (False)

Bus Slave Ports

This model has the following bus slave ports:

Bus Slave Port: bport1

Table 1: Bus Slave Port: bport1

NameSize (bytes)Must Be ConnectedDescription
bport10x2000F (False)

Table 2: Bus Slave Port: bport1 Registers:

NameOffsetWidth (bits)DescriptionR/Wis Volatile
ab_SOPT10x032System Options Register 1, offset: 0x0
ab_SOPT1CFG0x432SOPT1 Configuration Register, offset: 0x4
ab_SOPT20x100432System Options Register 2, offset: 0x1004
ab_SOPT40x100c32System Options Register 4, offset: 0x100C
ab_SOPT50x101032System Options Register 5, offset: 0x1010
ab_SOPT60x101432System Options Register 6, offset: 0x1014
ab_SOPT70x101832System Options Register 7, offset: 0x1018
ab_SDID0x102432System Device Identification Register, offset: 0x1024
ab_SCGC10x102832System Clock Gating Control Register 1, offset: 0x1028
ab_SCGC20x102c32System Clock Gating Control Register 2, offset: 0x102C
ab_SCGC30x103032System Clock Gating Control Register 3, offset: 0x1030
ab_SCGC40x103432System Clock Gating Control Register 4, offset: 0x1034
ab_SCGC50x103832System Clock Gating Control Register 5, offset: 0x1038
ab_SCGC60x103c32System Clock Gating Control Register 6, offset: 0x103C
ab_SCGC70x104032System Clock Gating Control Register 7, offset: 0x1040
ab_CLKDIV10x104432System Clock Divider Register 1, offset: 0x1044
ab_CLKDIV20x104832System Clock Divider Register 2, offset: 0x1048
ab_FCFG10x104c32Flash Configuration Register 1, offset: 0x104C
ab_FCFG20x105032Flash Configuration Register 2, offset: 0x1050
ab_UIDH0x105432Unique Identification Register High, offset: 0x1054
ab_UIDMH0x105832Unique Identification Register Mid-High, offset: 0x1058
ab_UIDML0x105c32Unique Identification Register Mid Low, offset: 0x105C
ab_UIDL0x106032Unique Identification Register Low, offset: 0x1060
ab_CLKDIV40x106832System Clock Divider Register 4, offset: 0x1068
ab_MCR0x106c32Misc Control Register, offset: 0x106C

Platforms that use this peripheral component

Peripheral components can be used in many different platforms, including those developed by Imperas or by other users of OVP. You can use this peripheral in your own platforms.

Table 3: Publicly available platforms using peripheral 'KinetisSIM'

Platform NameVendor

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