Name | Type | Must Be Connected | Description |
---|---|---|---|
Reset | input | F (False) |
Table : Net Ports
Name | Type | Must Be Connected | Description |
---|---|---|---|
Reset | input | F (False) |
Table 1: Bus Slave Port: bport1
Name | Size (bytes) | Must Be Connected | Description |
---|---|---|---|
bport1 | 0x1000 | F (False) |
Table 2: Bus Slave Port: bport1 Registers:
Name | Offset | Width (bits) | Description | R/W | is Volatile |
---|---|---|---|---|---|
ab_MCR | 0x0 | 32 | DSPI Module Configuration Register, offset: 0x0 | ||
ab_TCR | 0x8 | 32 | DSPI Transfer Count Register, offset: 0x8 | ||
ab_CTAR0 | 0xc | 32 | DSPI Clock and Transfer Attributes Register 0, Master/Slave modes, offset 0x0c | ||
ab_CTAR1 | 0x10 | 32 | DSPI Clock and Transfer Attributes Register 1, Master mode, offset 0x10 | ||
ab_SR | 0x2c | 32 | DSPI Status Register, offset: 0x2C | ||
ab_RSER | 0x30 | 32 | DSPI DMA/Interrupt Request Select and Enable Register, offset: 0x30 | ||
ab_PUSHR | 0x34 | 32 | DSPI PUSH TX FIFO Register In Master Mode, offset: 0x34 | ||
ab_POPR | 0x38 | 32 | DSPI POP RX FIFO Register, offset: 0x38 | ||
ab_TXFR0 | 0x3c | 32 | DSPI Transmit FIFO Registers, offset: 0x3C | ||
ab_TXFR1 | 0x40 | 32 | DSPI Transmit FIFO Registers, offset: 0x40 | ||
ab_TXFR2 | 0x44 | 32 | DSPI Transmit FIFO Registers, offset: 0x44 | ||
ab_TXFR3 | 0x48 | 32 | DSPI Transmit FIFO Registers, offset: 0x48 | ||
ab_RXFR0 | 0x7c | 32 | DSPI Receive FIFO Registers, offset: 0x7C | ||
ab_RXFR1 | 0x80 | 32 | DSPI Receive FIFO Registers, offset: 0x80 | ||
ab_RXFR2 | 0x84 | 32 | DSPI Receive FIFO Registers, offset: 0x84 | ||
ab_RXFR3 | 0x88 | 32 | DSPI Receive FIFO Registers, offset: 0x88 |
Table 3: Publicly available platforms using peripheral 'KinetisSPI'