OVP Peripheral Model: FreescaleUart

Model Specific Information

This page provides introductory usage information for an Imperas OVP peripheral behavioral model. The page is split into sections providing specific information for this peripheral, including any ports for connecting into a platform, registers, other component parts, and configuration options and general information for peripheral modeling with Imperas OVP.


Open Source Apache 2.0


Error conditions, DMA, ISO7816 mode and Wake up are not supported.


Freescale UART - Supports interrupts and fifos.


Freescale Kinetis Peripheral User Guide


The Uart peripheral model is located in an Imperas/OVP installation at the VLNV: / peripheral / Uart / 1.0.

Peripheral Instance Parameters

This model accepts the following parameters:

Table : Peripheral Parameters

connectnonblockingboolIf set, simulation can begin before the connection is made
finishOnDisconnectboolIf set, disconnecting the port will cause the simulation to finish
logboolIf specified, serial output will go to simulator log
portFilestringIf portnum was specified as zero, write the port number to this file when it's known
outfilestringName of file to write device output
infilestringName of file to use for device source
portnumuns32If set, listen on this port. If set to zero, allocate a port from the pool and listen on that.
consoleboolIf specified, port number is ignored, and a console pops up automatically
moduleClkFrequns32Frequency (in hertz) of module clock used in baud rate calculation (default=10.2 MHz)
fifoSizeuns32Size of fifos (default 128)
directReadWriteboolEnable the use of the DirectRead and DirectWrite connections
xcharsuns32Width of console in characters
ycharsuns32Height of console in characters
recordstringRecord external events into this file
replaystringReplay external events from this file

Net Ports

This model has the following net ports:

Table 1: Net Ports

NameTypeMust Be ConnectedDescription
InterruptoutputF (False)
DirectReadinputF (False)
DirectWriteoutputF (False)
ResetinputF (False)

Bus Slave Ports

This model has the following bus slave ports:

Bus Slave Port: bport1

Table 2: Bus Slave Port: bport1

NameSize (bytes)Must Be ConnectedDescription
bport10x1000F (False)

Table 3: Bus Slave Port: bport1 Registers:

NameOffsetWidth (bits)DescriptionR/Wis Volatile
ab_twfifo0x138UART FIFO Transmit Watermark Register
ab_sfifo0x128UART FIFO Status Register
ab_cfifo0x118UART FIFO Control Register
ab_pfifo0x108UART FIFO Parameters Register
ab_infrared0xe8UART Infrared Register
ab_modem0xd8UART Modem Register
ab_ed0xc8UART Extended Data Register
ab_c50xb8UART Control Register 5
ab_c40xa8UART Control Register 4
ab_ma20x98UART Match Address Registers 2
ab_ma10x88UART Match Address Registers 1
ab_d0x78UART Data Register
ab_c30x68UART Control Register 3
ab_s20x58UART Status Register 2
ab_s10x48UART Status Register 1
ab_c20x38UART Control Register 2
ab_c10x28UART Control Register 1
ab_bdl0x18UART Baud Rate Registers:Low
ab_bdh0x08UART Baud Rate Registers:High
ab_tcfifo0x148UART FIFO Transmit Count Register
ab_rwfifo0x158UART FIFO Receive Watermark Register
ab_rcfifo0x168UART FIFO Receive Count Register

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