OVP Peripheral Model: FreescaleUart
Model Specific Information
This page provides introductory usage information for an Imperas OVP peripheral behavioral model.
The page is split into sections providing specific information for this peripheral,
including any ports for connecting into a platform, registers, other component parts, and configuration options and general information for peripheral modeling with Imperas OVP.
Description
Freescale UART - Supports interrupts and fifos.
Limitations
Error conditions, DMA, ISO7816 mode and Wake up are not supported.
Licensing
Open Source Apache 2.0
Reference
Freescale Kinetis Peripheral User Guide
Location
The Uart peripheral model is located in an Imperas/OVP installation at the VLNV: freescale.ovpworld.org / peripheral / Uart / 1.0.
Peripheral Instance Parameters
This model accepts the following parameters:
Table : Peripheral Parameters
Name | Type | Description |
---|
directReadWrite | bool | Enable the use of the DirectRead and DirectWrite connections |
fifoSize | uns32 | Size of fifos (default 128) |
moduleClkFreq | uns32 | Frequency (in hertz) of module clock used in baud rate calculation (default=10.2 MHz) |
console | bool | If specified, port number is ignored, and a console pops up automatically |
client | bool | If true, model is a client and will connect to portnum. If false, model is a server and will listen on portnum. |
portnum | uns32 | If set, listen on, or connect to, this port. If set to zero in listen mode, allocate a port from the pool and listen on that. |
hostname | string | Name (or IP address) of host to connect to. Valid if listen=true |
infile | string | Name of file to use for device source |
outfile | string | Name of file to write device output |
portFile | string | If portnum was specified as zero, write the port number to this file when it's known |
log | bool | If specified, serial output will go to simulator log |
finishOnDisconnect | bool | If set, disconnecting the port will cause the simulation to finish |
connectnonblocking | bool | If set, simulation can begin before the connection is made |
xchars | uns32 | Width of console in characters |
ychars | uns32 | Height of console in characters |
record | string | Record external events into this file |
replay | string | Replay external events from this file |
Net Ports
This model has the following net ports:
Table 1: Net Ports
Name | Type | Must Be Connected | Description |
---|
DirectWrite | output | F (False) | |
DirectRead | input | F (False) | |
Interrupt | output | F (False) | |
Reset | input | F (False) | |
Bus Slave Ports
This model has the following bus slave ports:
Bus Slave Port: bport1
Table 2: Bus Slave Port: bport1
Name | Size (bytes) | Must Be Connected | Description |
---|
bport1 | 0x1000 | F (False) | |
Table 3: Bus Slave Port: bport1 Registers:
Name | Offset | Width (bits) | Description | R/W | is Volatile |
---|
ab_bdh | 0x0 | 8 | UART Baud Rate Registers:High | | |
ab_bdl | 0x1 | 8 | UART Baud Rate Registers:Low | | |
ab_c1 | 0x2 | 8 | UART Control Register 1 | | |
ab_c2 | 0x3 | 8 | UART Control Register 2 | | |
ab_s1 | 0x4 | 8 | UART Status Register 1 | | |
ab_s2 | 0x5 | 8 | UART Status Register 2 | | |
ab_c3 | 0x6 | 8 | UART Control Register 3 | | |
ab_d | 0x7 | 8 | UART Data Register | | |
ab_ma1 | 0x8 | 8 | UART Match Address Registers 1 | | |
ab_ma2 | 0x9 | 8 | UART Match Address Registers 2 | | |
ab_c4 | 0xa | 8 | UART Control Register 4 | | |
ab_c5 | 0xb | 8 | UART Control Register 5 | | |
ab_ed | 0xc | 8 | UART Extended Data Register | | |
ab_modem | 0xd | 8 | UART Modem Register | | |
ab_infrared | 0xe | 8 | UART Infrared Register | | |
ab_pfifo | 0x10 | 8 | UART FIFO Parameters Register | | |
ab_cfifo | 0x11 | 8 | UART FIFO Control Register | | |
ab_sfifo | 0x12 | 8 | UART FIFO Status Register | | |
ab_twfifo | 0x13 | 8 | UART FIFO Transmit Watermark Register | | |
ab_tcfifo | 0x14 | 8 | UART FIFO Transmit Count Register | | |
ab_rwfifo | 0x15 | 8 | UART FIFO Receive Watermark Register | | |
ab_rcfifo | 0x16 | 8 | UART FIFO Receive Count Register | | |