OVP Peripheral Model: FreescaleVybridANADIG

Model Specific Information

This page provides introductory usage information for an Imperas OVP peripheral behavioral model. The page is split into sections providing specific information for this peripheral, including any ports for connecting into a platform, registers, other component parts, and configuration options and general information for peripheral modeling with Imperas OVP.


Analog components control digital interface


Only models pll_lock register read


Open Source Apache 2.0


Freescale Vybrid Peripheral User Guide


The VybridANADIG peripheral model is located in an Imperas/OVP installation at the VLNV: / peripheral / VybridANADIG / 1.0.

Net Ports

This model has the following net ports:

Table : Net Ports

NameTypeMust Be ConnectedDescription
ResetinputF (False)

Bus Slave Ports

This model has the following bus slave ports:

Bus Slave Port: bport1

Table 1: Bus Slave Port: bport1

NameSize (bytes)Must Be ConnectedDescription
bport10x1000F (False)

Table 2: Bus Slave Port: bport1 Registers:

NameOffsetWidth (bits)DescriptionR/Wis Volatile
ab_pll_lock0x2c032ANADIG PLL Lock Register

Platforms that use this peripheral component

Peripheral components can be used in many different platforms, including those developed by Imperas or by other users of OVP. You can use this peripheral in your own platforms.

Table 3: Publicly available platforms using peripheral 'VybridANADIG'

Platform NameVendor

Page was generated in 0.0212 seconds