OVP Peripheral Model: FreescaleVybridI2C

Model Specific Information

This page provides introductory usage information for an Imperas OVP peripheral behavioral model. The page is split into sections providing specific information for this peripheral, including any ports for connecting into a platform, registers, other component parts, and configuration options and general information for peripheral modeling with Imperas OVP.


Model of the I2C peripheral used on the Freescale Vybrid platform


Provides the base behaviour for the OVP Freescale Vybrid platforms


Development based on document number: VYBRIDRM Rev. 5, 07/2013


Open Source Apache 2.0


The VybridI2C peripheral model is located in an Imperas/OVP installation at the VLNV: / peripheral / VybridI2C / 1.0.

Net Ports

This model has the following net ports:

Table : Net Ports

NameTypeMust Be ConnectedDescription
ResetinputF (False)

Bus Slave Ports

This model has the following bus slave ports:

Bus Slave Port: bport1

Table 1: Bus Slave Port: bport1

NameSize (bytes)Must Be ConnectedDescription
bport10x1000F (False)

Table 2: Bus Slave Port: bport1 Registers:

NameOffsetWidth (bits)DescriptionR/Wis Volatile
ab_IBAD0x08I2C Bus Address Register, offset: 0x0
ab_IBFD0x18I2C Bus Frequency Divider Register, offset: 0x1
ab_IBCR0x28I2C Bus Control Register, offset: 0x2
ab_IBSR0x38I2C Bus Status Register, offset: 0x3
ab_IBDR0x48I2C Bus Data I/O Register, offset: 0x4
ab_IBIC0x58I2C Bus Interrupt Config Register, offset: 0x5
ab_IBDBG0x68I2C Bus Debug Register, offset: 0x6

Platforms that use this peripheral component

Peripheral components can be used in many different platforms, including those developed by Imperas or by other users of OVP. You can use this peripheral in your own platforms.

Table 3: Publicly available platforms using peripheral 'VybridI2C'

Platform NameVendor

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