OVP Peripheral Model: FreescaleVybridSDHC

Model Specific Information

This page provides introductory usage information for an Imperas OVP peripheral behavioral model. The page is split into sections providing specific information for this peripheral, including any ports for connecting into a platform, registers, other component parts, and configuration options and general information for peripheral modeling with Imperas OVP.


Model of the SDHC peripheral used on the Freescale Vybrid platform


Provides the base behaviour for the OVP Freescale Vybrid platforms


Development based on document number: VYBRIDRM Rev. 5, 07/2013


Open Source Apache 2.0


The VybridSDHC peripheral model is located in an Imperas/OVP installation at the VLNV: / peripheral / VybridSDHC / 1.0.

Net Ports

This model has the following net ports:

Table : Net Ports

NameTypeMust Be ConnectedDescription
ResetinputF (False)

Bus Slave Ports

This model has the following bus slave ports:

Bus Slave Port: bport1

Table 1: Bus Slave Port: bport1

NameSize (bytes)Must Be ConnectedDescription
bport10x1000F (False)

Table 2: Bus Slave Port: bport1 Registers:

NameOffsetWidth (bits)DescriptionR/Wis Volatile
ab_DSADDR0x032DMA System Address Register, offset: 0x0
ab_BLKATTR0x432Block Attributes Register, offset: 0x4
ab_CMDARG0x832Command Argument Register, offset: 0x8
ab_XFERTYP0xc32Transfer Type Register, offset: 0xC
ab_CMDRSP00x1032Command Response 0, offset: 0x10, array step: 0x4
ab_CMDRSP10x1432Command Response 1, offset: 0x10, array step: 0x4
ab_CMDRSP20x1832Command Response 2, offset: 0x10, array step: 0x4
ab_CMDRSP30x1c32Command Response 3, offset: 0x10, array step: 0x4
ab_DATPORT0x2032Buffer Data Port Register, offset: 0x20
ab_PRSSTAT0x2432Present State Register, offset: 0x24
ab_PROCTL0x2832Protocol Control Register, offset: 0x28
ab_SYSCTL0x2c32System Control Register, offset: 0x2C
ab_IRQSTAT0x3032Interrupt Status Register, offset: 0x30
ab_IRQSTATEN0x3432Interrupt Status Enable Register, offset: 0x34
ab_IRQSIGEN0x3832Interrupt Signal Enable Register, offset: 0x38
ab_AC12ERR0x3c32Auto CMD12 Error Status Register, offset: 0x3C
ab_HTCAPBLT0x4032Host Controller Capabilities, offset: 0x40
ab_WML0x4432Watermark Level Register, offset: 0x44
ab_FEVT0x5032Force Event Register, offset: 0x50
ab_ADMAES0x5432ADMA Error Status Register, offset: 0x54
ab_ADSADDR0x5832ADMA System Address Register, offset: 0x58
ab_VENDOR0xc032Vendor Specific Register, offset: 0xC0
ab_MMCBOOT0xc432MMC Boot Register, offset: 0xC4
ab_HOSTVER0xfc32Host Controller Version, offset: 0xFC

Platforms that use this peripheral component

Peripheral components can be used in many different platforms, including those developed by Imperas or by other users of OVP. You can use this peripheral in your own platforms.

Table 3: Publicly available platforms using peripheral 'VybridSDHC'

Platform NameVendor

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