OVP Peripheral Model: FreescaleVybridSPI

Model Specific Information

This page provides introductory usage information for an Imperas OVP peripheral behavioral model. The page is split into sections providing specific information for this peripheral, including any ports for connecting into a platform, registers, other component parts, and configuration options and general information for peripheral modeling with Imperas OVP.


Model of the SPI peripheral used on the Freescale Vybrid platform


Provides the base behaviour for the OVP Freescale Vybrid platforms


Development based on document number: VYBRIDRM Rev. 5, 07/2013


Open Source Apache 2.0


The VybridSPI peripheral model is located in an Imperas/OVP installation at the VLNV: / peripheral / VybridSPI / 1.0.

Net Ports

This model has the following net ports:

Table : Net Ports

NameTypeMust Be ConnectedDescription
ResetinputF (False)

Bus Slave Ports

This model has the following bus slave ports:

Bus Slave Port: bport1

Table 1: Bus Slave Port: bport1

NameSize (bytes)Must Be ConnectedDescription
bport10x1000F (False)

Table 2: Bus Slave Port: bport1 Registers:

NameOffsetWidth (bits)DescriptionR/Wis Volatile
ab_MCR0x032Module Configuration Register, offset: 0x0
ab_TCR0x832Transfer Count Register, offset: 0x8
ab_CTAR0xc32DSPI Clock and Transfer Attributes Register (In Master Mode)
ab_SR0x2c32DSPI Status Register, offset: 0x2C
ab_RSER0x3032DMA/Interrupt Request Select and Enable Register, offset: 0x30
ab_PUSHR0x3432PUSH TX FIFO Register In Master Mode, offset: 0x34
ab_POPR0x3832POP RX FIFO Register, offset: 0x38
ab_TXFR0x3c32DSPI Transmit FIFO Registers
ab_RXFR0x7c32DSPI Receive FIFO Registers

Platforms that use this peripheral component

Peripheral components can be used in many different platforms, including those developed by Imperas or by other users of OVP. You can use this peripheral in your own platforms.

Table 3: Publicly available platforms using peripheral 'VybridSPI'

Platform NameVendor

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