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GhsMulti



OVP Virtual Platform: ghs-multi

This page provides detailed information about the OVP Virtual Platform Model of the renesas.ovpworld.org ghs-multi platform.

Description

Platform Compatible with Greenhills Compiler Output for a V850E1 Processor. The bare metal platform instantiates a single V850 processor instance. The processor operate using big endian data ordering. It creates contiguous memory from 0x00000000 to 0xFFFFFFFF. The ICM platform can be passed any application compiled to an V850 elf format. ./platform..exe --program application.elf

Licensing

Open Source Apache 2.0

Limitations

BareMetal platform to support images generated with Greenhills Compiler targeting a V850E1 Processor

Reference

R01UH0128ED0700, Rev. 7.00, Oct 06, 2010

Location

The ghs-multi virtual platform is located in an Imperas/OVP installation at the VLNV: renesas.ovpworld.org / module / ghs-multi / 1.0.

Platform Summary

Table : Components in platform

TypeInstanceVendorComponent
Processorcpu1renesas.ovpworld.orgv850V850E1
Memorymemoryovpworld.orgram
Busbus1(builtin)address width:32

Platform Simulation Attributes

Table 1: Platform Simulation Attributes

AttributeValueDescription
stoponctrlcstoponctrlcStop on control-C



Processor [renesas.ovpworld.org/processor/v850/1.0] instance: cpu1

Processor model type: 'v850' variant 'V850E1' definition

Imperas OVP processor models support multiple variants and details of the variants implemented in this model can be found in:
- the Imperas installation located at ImperasLib/source/renesas.ovpworld.org/processor/v850/1.0/doc
- the OVP website: OVP_Model_Specific_Information_v850_V850E1.pdf

Description

V850 Family Processor Model.

Licensing

Open Source Apache 2.0

Limitations

The following Debug Registers are non-functional DIR, BPC0, BPC1, ASID BPAV0, BPAV1, BPAM0, BPAM1 BPDV0, BPDV1, BPDM0, BPDM1

Verification

Models have been extensively tested by Imperas, In addition Verification suites have been supplied by Renesas for Feature Set validation

Features

All v850e1 Instructions are supported.
All Program and System Registers are supported.

Instance Parameters

Several parameters can be specified when a processor is instanced in a platform. For this processor instance 'cpu1' it has been instanced with the following parameters:

Table 2: Processor Instance 'cpu1' Parameters (Configurations)

ParameterValueDescription
mips100The nominal MIPS for the processor
semihostnamev850NewlibThe VLNV name of a Semihost library

Table 3: Processor Instance 'cpu1' Parameters (Attributes)

Parameter NameValueType
variantV850E1enum

Memory Map for processor 'cpu1' bus: 'bus1'

Processor instance 'cpu1' is connected to bus 'bus1' using master port 'INSTRUCTION'.

Processor instance 'cpu1' is connected to bus 'bus1' using master port 'DATA'.

Table 4: Memory Map ( 'cpu1' / 'bus1' [width: 32] )

Lo AddressHi AddressInstanceComponent
0x00xFFFFFFFFmemoryram

Net Connections to processor: 'cpu1'

There are no nets connected to this processor.


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