OVP Peripheral Model: Intel82077AA
Model Specific Information
This page provides introductory usage information for an Imperas OVP peripheral behavioral model.
The page is split into sections providing specific information for this peripheral,
including any ports for connecting into a platform, registers, other component parts, and configuration options and general information for peripheral modeling with Imperas OVP.
Licensing
Open Source Apache 2.0
Description
Dummy Floppy Disc Controller.
Limitations
Register stubs only.
Reference
http://www.buchty.net/casio/files/82077.pdf http://www.alldatasheet.com/datesheet-pdf/pdf/167793/INTEL/82077AA.html
Location
The 82077AA peripheral model is located in an Imperas/OVP installation at the VLNV: intel.ovpworld.org / peripheral / 82077AA / 1.0.
Bus Slave Ports
This model has the following bus slave ports:
Bus Slave Port: bport1
Table : Bus Slave Port: bport1
Name | Size (bytes) | Must Be Connected | Description |
---|
bport1 | 0x8 | T (True) | Byte:wide access to control and status registers. |
Table 1: Bus Slave Port: bport1 Registers:
Name | Offset | Width (bits) | Description | R/W | is Volatile |
---|
sra | 0x0 | 8 | Status Register A | | |
srb | 0x1 | 8 | Status Register B | | |
dor | 0x2 | 8 | Digital Out Register | | |
tdr | 0x3 | 8 | Tape Drive Register | | |
msr | 0x4 | 8 | Main Status Register | | |
dsr | 0x4 | 8 | Data Rate Select Register | | |
fifo | 0x5 | 8 | Data Fifo | | |
reserved | 0x6 | 8 | Reserved | | |
dir | 0x7 | 8 | Digital Input Register | | |
ccr | 0x7 | 8 | Configuration Control Register | | |
Platforms that use this peripheral component
Peripheral components can be used in many different platforms, including those developed by Imperas or by other users of OVP. You can use this peripheral in your own platforms.
Table 2: Publicly available platforms using peripheral '82077AA'