OVP Peripheral Model: Intel8253
Model Specific Information
This page provides introductory usage information for an Imperas OVP peripheral behavioral model.
The page is split into sections providing specific information for this peripheral,
including any ports for connecting into a platform, registers, other component parts, and configuration options and general information for peripheral modeling with Imperas OVP.
Licensing
Open Source Apache 2.0
Limitations
This model has sufficient functionality to allow a Linux Kernel to Boot on the MIPS:MALTA platform. Not all modes are supported.
Description
Intel 8253 Programmable Interval Timer (PIT)
Reference
Intel 8253 Datasheet. MIPS Malta Platform Reference Guide.
Location
The 8253 peripheral model is located in an Imperas/OVP installation at the VLNV: intel.ovpworld.org / peripheral / 8253 / 1.0.
Net Ports
This model has the following net ports:
Table : Net Ports
Name | Type | Must Be Connected | Description |
---|
out2 | output | F (False) | |
gate2 | input | F (False) | |
clk2 | input | F (False) | |
out1 | output | F (False) | |
gate1 | input | F (False) | |
clk1 | input | F (False) | |
out0 | output | F (False) | |
gate0 | input | F (False) | |
clk0 | input | F (False) | |
Bus Slave Ports
This model has the following bus slave ports:
Bus Slave Port: bport1
Table 1: Bus Slave Port: bport1
Name | Size (bytes) | Must Be Connected | Description |
---|
bport1 | 0x4 | F (False) | |
Table 2: Bus Slave Port: bport1 Registers:
Name | Offset | Width (bits) | Description | R/W | is Volatile |
---|
reg_CNTL | 0x3 | 8 | | | |
reg_CTR2 | 0x2 | 8 | | | |
reg_CTR1 | 0x1 | 8 | | | |
reg_CTR0 | 0x0 | 8 | | | |
Platforms that use this peripheral component
Peripheral components can be used in many different platforms, including those developed by Imperas or by other users of OVP. You can use this peripheral in your own platforms.
Table 3: Publicly available platforms using peripheral '8253'