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Mips1004Kf

Model Information


This page provides detailed information about the OVP Fast Processor Model of the MIPS 1004Kf core.
Processor IP owner is MIPS. More information is available from them here.

OVP Fast Processor Model is written in C.
Provides a C API for use in C based platforms.
Provides a native C++ interface for use in SystemC TLM2 platforms.

The model is written using the OVP VMI API that provides a Virtual Machine Interface that defines the behavior of the processor.
The VMI API makes a clear line between model and simulator allowing very good optimization and world class high speed performance.

The model is provided as a binary shared object and is also available as source (different models have different licensing conditions). This allows the download and use of the model binary or the use of the source to explore and modify the model.

The model has been run through an extensive QA and regression testing process.

Parallel Simulation using Imperas QuantumLeap


Traditionally, processor models and simulators make use of one thread on the host PC. Imperas have developed a technology, called QuantumLeap, that makes use of the many host cores found in modern PC/workstations to achieve industry leading simulation performance. To find out about the Imperas parallel simulation lookup Imperas QuantumLeap. There are videos of QuantumLeap on ARM here, and MIPS here. For press information related to QuantumLeap for ARM click here or for MIPS click here.
Many of the OVP Fast Processor Models have been qualified to work with QuantumLeap - this is indicated for this model below.

Embedded Software Development tools


This model executes instructions of the target architecture and provides an interface for debug access. An interface to GDB is provided and this allows the connection of many industry standard debuggers that use the GDB/RSP interface. For more information watch the OVP video here.
The model also works with the Imperas Multicore Debugger and advanced Verification, Analysis and Profiling tools.

Instruction Set Simulator (ISS) for MIPS 1004Kf


An ISS is a software development tool that takes in instructions for a target processor and executes them. The heart of an ISS is the model of the processor. Imperas has developed a range of ISS products for use in embedded software development that utilize this fast Fast Processor Model. The Imperas MIPS 1004Kf ISS runs on Windows/Linux x86 systems and takes a cross compiled elf file of your program and allows very fast execution. The MIPS 1004Kf ISS also provides access to standard GDB/RSP debuggers and connects to the Eclipse IDE and Imperas debuggers.

Overview of MIPS 1004Kf Fast Processor Model


Model Variant name: 1004Kf
Description:
    MIPS32 Configurable Processor Model
Licensing:
    Usage of binary model under license governing simulator usage. Source of model available under Imperas Software License Agreement.
Limitations:
    If this model is not part of your installation, then it is available for download from www.OVPworld.org/MIPSuser.
    Cache model does not implement coherency
Verification:
    Models have been validated correct as part of the MIPS Verified program and run through the MIPS AVP test programs
Features:
    only MIPS32 Instruction set implemented
    MMU Type: Standard TLB
    FPU implemented
    L1 I and D cache model in either full or tag-only mode implemented (disabled by default)
    Vectored interrupts implemented
    MIPS16e ASE implemented
    MT ASE implemented
    DSP ASE implemented

Model downloadable (needs registration and to be logged in) in package mips32.model for Windows32 and for Linux32
OVP simulator downloadable (needs registration and to be logged in) in package OVPsim for Windows32 and for Linux32
OVP Download page here.
OVP documentation that provides overview information on processor models is available OVP_Guide_To_Using_Processor_Models.pdf.

Full model specific documentation on the variant 1004Kf is available OVP_Model_Specific_Information_mips32_r1r5_1004Kf.pdf.

Configuration


Location: The Fast Processor Model source and object file is found in the installation VLNV tree: mips.ovpworld.org/processor/mips32_r1r5/1.0
Processor Endian-ness: This model can be set to either endian-ness (normally by a pin, or the ELF code).
Processor ELF Code: The ELF code for this model is: 0x8
QuantumLeap Support: The processor model is qualified to run in a QuantumLeap enabled simulator.

TLM Initiator Ports (Bus Ports)

Port TypeNameWidth (bits)Description
masterINSTRUCTION12
masterDATA12

SystemC Signal Ports (Net Ports)

Port TypeNameDescription
resetinput
dintinput
int0input
int1input
int2input
int3input
int4input
int5input
int6input
int7input
int8input
int9input
int10input
int11input
int12input
int13input
int14input
int15input
int16input
int17input
int18input
int19input
int20input
int21input
int22input
int23input
int24input
int25input
int26input
int27input
int28input
int29input
int30input
int31input
int32input
int33input
int34input
int35input
int36input
int37input
int38input
int39input
yq_CPU0input
yq0_CPU0input
yq1_CPU0input
yq2_CPU0input
yq3_CPU0input
yq4_CPU0input
yq5_CPU0input
yq6_CPU0input
yq7_CPU0input
yq8_CPU0input
yq9_CPU0input
yq10_CPU0input
yq11_CPU0input
yq12_CPU0input
yq13_CPU0input
yq14_CPU0input
yq15_CPU0input
hwint0_CPU0_VPE0input
hwint1_CPU0_VPE0input
hwint2_CPU0_VPE0input
hwint3_CPU0_VPE0input
hwint4_CPU0_VPE0input
hwint5_CPU0_VPE0input
nmi_CPU0_VPE0input
hwint0input
vc_run_CPU0_VPE0input
hwint0_CPU0_VPE1input
hwint1_CPU0_VPE1input
hwint2_CPU0_VPE1input
hwint3_CPU0_VPE1input
hwint4_CPU0_VPE1input
hwint5_CPU0_VPE1input
nmi_CPU0_VPE1input
vc_run_CPU0_VPE1input
yq_CPU1input
yq0_CPU1input
yq1_CPU1input
yq2_CPU1input
yq3_CPU1input
yq4_CPU1input
yq5_CPU1input
yq6_CPU1input
yq7_CPU1input
yq8_CPU1input
yq9_CPU1input
yq10_CPU1input
yq11_CPU1input
yq12_CPU1input
yq13_CPU1input
yq14_CPU1input
yq15_CPU1input
hwint0_CPU1_VPE0input
hwint1_CPU1_VPE0input
hwint2_CPU1_VPE0input
hwint3_CPU1_VPE0input
hwint4_CPU1_VPE0input
hwint5_CPU1_VPE0input
nmi_CPU1_VPE0input
vc_run_CPU1_VPE0input
hwint0_CPU1_VPE1input
hwint1_CPU1_VPE1input
hwint2_CPU1_VPE1input
hwint3_CPU1_VPE1input
hwint4_CPU1_VPE1input
hwint5_CPU1_VPE1input
nmi_CPU1_VPE1input
vc_run_CPU1_VPE1input
yq_CPU2input
yq0_CPU2input
yq1_CPU2input
yq2_CPU2input
yq3_CPU2input
yq4_CPU2input
yq5_CPU2input
yq6_CPU2input
yq7_CPU2input
yq8_CPU2input
yq9_CPU2input
yq10_CPU2input
yq11_CPU2input
yq12_CPU2input
yq13_CPU2input
yq14_CPU2input
yq15_CPU2input
hwint0_CPU2_VPE0input
hwint1_CPU2_VPE0input
hwint2_CPU2_VPE0input
hwint3_CPU2_VPE0input
hwint4_CPU2_VPE0input
hwint5_CPU2_VPE0input
nmi_CPU2_VPE0input
vc_run_CPU2_VPE0input
hwint0_CPU2_VPE1input
hwint1_CPU2_VPE1input
hwint2_CPU2_VPE1input
hwint3_CPU2_VPE1input
hwint4_CPU2_VPE1input
hwint5_CPU2_VPE1input
nmi_CPU2_VPE1input
vc_run_CPU2_VPE1input
yq_CPU3input
yq0_CPU3input
yq1_CPU3input
yq2_CPU3input
yq3_CPU3input
yq4_CPU3input
yq5_CPU3input
yq6_CPU3input
yq7_CPU3input
yq8_CPU3input
yq9_CPU3input
yq10_CPU3input
yq11_CPU3input
yq12_CPU3input
yq13_CPU3input
yq14_CPU3input
yq15_CPU3input
hwint0_CPU3_VPE0input
hwint1_CPU3_VPE0input
hwint2_CPU3_VPE0input
hwint3_CPU3_VPE0input
hwint4_CPU3_VPE0input
hwint5_CPU3_VPE0input
nmi_CPU3_VPE0input
vc_run_CPU3_VPE0input
hwint0_CPU3_VPE1input
hwint1_CPU3_VPE1input
hwint2_CPU3_VPE1input
hwint3_CPU3_VPE1input
hwint4_CPU3_VPE1input
hwint5_CPU3_VPE1input
nmi_CPU3_VPE1input
vc_run_CPU3_VPE1input

No FIFO Ports in 1004Kf.


Exceptions

NameCodeDescription
Int0
Mod1
TLBL2
TLBS3
AdEL4
AdES5
IBE6
DBE7
Sys8
Bp9
RI10
CpU11
Ov12
Tr13
FPE15
Impl116
Impl217
C2E18
TLBRI19
TLBXI20
MDMX22
WATCH23
MCheck24
Thread25
DSPDis26
Prot29
CacheErr30

Execution Modes

ModeCodeDescription
KERNEL0
DEBUG1
SUPERVISOR2
USER3

More Detailed Information

The 1004Kf OVP Fast Processor Model also has parameters, model commands, and many registers.
The model may also have hierarchy or be multicore and have other attributes and capabilities.
To see this information, please have a look at the model variant specific documents.
Click here to see the detailed document OVP_Model_Specific_Information_mips32_r1r5_1004Kf.pdf.

Other Sites/Pages with similar information

Information on the 1004Kf OVP Fast Processor Model can also be found on other web sites:
www.imperas.com has more information on the model library.



MipsProcessors
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