OVP Virtual Platform: BareMetalMips32Dual
What is a Bare Metal Platform?
A 'Bare Metal' Platform consists of a single processor with memory available over its complete address range.
This is ideal for execution of a user application that has been compiled for the target processor core using cross-compilation.
Obtaining the BareMetalMips32Dual platform and the OVP Simulator
The source and binary of the bare metal platforms are part of the OVP/Imperas downloads and live on a VLNV (Vendor Library Name Version) path.
To download from OVPworld, browse the OVP downloads page and download the OVPsim package.
Click here to browse available downloads.When installed this platform is found in your installation here:
ImperasLib/source/mips.ovpworld.org/platform/BareMetalMips32Dual/1.0.
Running the Bare Metal Platform
1. Run the installer to install into a local directory on your PC.
We recommend you use a path without spaces, for example your home directory.
2. Enter the Demo Directory IMPERAS_HOME/Demo/BareMetalMips32Dual
3. On Windows, double-click on the batch file xx.bat and on Linux run the script xx.sh to run a simple application elf file on the Bare Metal Platform.
You will see output something like:
Info (ARM_NEWLIB_RDI_HEAP_INFO) RDI heap_base=0xc0000000
Hello
Info (ARM_NEWLIB_RDI_EXIT) Process has ended (exit)
Info
Info ---------------------------------------------------
Info CPU 'CPU1' STATISTICS
Info Type : arm
Info Nominal MIPS : 100
Info Final program counter : 0x91a4
Info Simulated instructions: 4,175
Info ---------------------------------------------------
Info
Info ---------------------------------------------------
Info SIMULATION TIME STATISTICS
Info Simulated time : 0.00 seconds
Info User time : 0.02 seconds
Info System time : 0.00 seconds
Info ---------------------------------------------------
Setting Up for Re-building the Application
To rebuild the application and create the elf file you will need 3 things:
- Cross-Compiler toolchain for thi processor
- An OVP Installation
- MSYS / MINGW environment (Windows Users Only)
Download and Installing the Cross-Compiler Toolchain
To download an appropriate tool chain, browse the OVP downloads page and download the package.
Click here to browse. If there is not one available please ask on the forum.
Once downloaded run the installer
<packageName>.Windows32.exe for Windows and <packageName>.Linux32.exe for Linux to install on your PC.
Installing MSYS / MINGW Environment (Windows Users Only)
Obtaining and installing the MSYS and MINGW environment is described in
Imperas_Installation_and_Getting_Started.pdf. Rebuilding
You will need to be in the Demo/'baremetaldemodir' directory using an MSYS shell for Windows or a Linux shell.
Re-building the Application>
make applicationRe-building the Bare Metal Platform>
make platformExecuting the application on the platformYou can just double click on the .bat file as done previously, or you can run from the msys command line:
>
./BareMetal.OS.exe hello.CROSS.elf
This page provides detailed information about the OVP Virtual Platform Model of the
mips.ovpworld.org BareMetalMips32Dual platform.
Description
Bare Metal Platform for a MIPS32 Processor (default 4Km).
The bare metal platform instantiates two MIPS32 processor instances.
The processor operates using big endian data ordering.
It creates contiguous memory from 0x00000000 to 0xFFFFFFFF.
The platform can be passed any application compiled to a MIPS elf format. The
same application executes on each processor. There is no sharing of data.
It may also be passed a new variant to be used (default 4Km)
./platform.OS.exe --program application.CROSS.elf [--variant
]
Licensing
Open Source Apache 2.0
Limitations
BareMetal platform for execution of MIPS MIPS32 binary files compiled with CodeSourcery CrossCompiler toolchain.
Location
The BareMetalMips32Dual virtual platform is located in an Imperas/OVP installation at the VLNV: mips.ovpworld.org / platform / BareMetalMips32Dual / 1.0.
Platform Summary
Table : Components in platform
Type | Instance | Vendor | Component | |
---|
Processor | cpu0 | mips.ovpworld.org | mips32_r1r5 | 4Km |
Processor | cpu1 | mips.ovpworld.org | mips32_r1r5 | 4Km |
Memory | memory0 | ovpworld.org | ram | |
Memory | memory1 | ovpworld.org | ram | |
Bus | bus0 | (builtin) | | address width:32 |
Bus | bus1 | (builtin) | | address width:32 |
Platform Simulation Attributes
Table 1: Platform Simulation Attributes
Attribute | Value | Description |
---|
stoponctrlc | stoponctrlc | Stop on control-C |
Command Line Control of the Platform
Built-in Arguments
Table 2: Platform Built-in Arguments
Attribute | Value | Description |
---|
allargs | allargs | The Command line parser will accept the complete imperas argument set. Note that this option is ignored in some Imperas products |
When running a platform in a Windows or Linux shell several command arguments can be specified. Typically there is a '-help' command which lists the commands available in the platforms.
For example: myplatform.exe -help
Some command line arguments require a value to be provided.
For example: myplatform.exe -program myimagefile.elf
Platform Specific Command Line Arguments
No platform specific command line arguments have been specified.
Processor [mips.ovpworld.org/processor/mips32_r1r5/1.0] instance: cpu0
Processor model type: 'mips32_r1r5' variant '4Km' definition
Imperas OVP processor models support multiple variants and details of the variants implemented in this model can be found in:
- the Imperas installation located at ImperasLib/source/mips.ovpworld.org/processor/mips32_r1r5/1.0/doc
- the OVP website: OVP_Model_Specific_Information_mips32_r1r5_4Km.pdf
Description
MIPS32 Configurable Processor Model
Licensing
Usage of binary model under license governing simulator usage. Source of model available under Imperas Software License Agreement.
Limitations
If this model is not part of your installation, then it is available for download from www.OVPworld.org/ip-vendor-mips.
Verification
Models have been validated correct as part of the MIPS Verified program and run through the MIPS AVP test programs
Features
only MIPS32 Instruction set implemented
MMU Type: Fixed Mapping
L1 I and D cache model in either full or tag-only mode implemented (disabled by default)
Instance Parameters
Several parameters can be specified when a processor is instanced in a platform. For this processor instance 'cpu0' it has been instanced with the following parameters:
Table 3: Processor Instance 'cpu0' Parameters (Configurations)
Parameter | Value | Description |
---|
endian | big | Select processor endian (big or little) |
mips | 100 | The nominal MIPS for the processor |
semihostvendor | mips.ovpworld.org | The VLNV vendor name of a Semihost library |
semihostname | mips32Newlib | The VLNV name of a Semihost library |
Table 4: Processor Instance 'cpu0' Parameters (Attributes)
Parameter Name | Value | Type |
---|
variant | 4Km | enum |
Memory Map for processor 'cpu0' bus: 'bus0'
Processor instance 'cpu0' is connected to bus 'bus0' using master port 'INSTRUCTION'.
Processor instance 'cpu0' is connected to bus 'bus0' using master port 'DATA'.
Table 5: Memory Map ( 'cpu0' / 'bus0' [width: 32] )
Lo Address | Hi Address | Instance | Component |
---|
0x0 | 0xFFFFFFFF | memory0 | ram |
Net Connections to processor: 'cpu0'
There are no nets connected to this processor.
Processor [mips.ovpworld.org/processor/mips32_r1r5/1.0] instance: cpu1
Processor model type: 'mips32_r1r5' variant '4Km' definition
Imperas OVP processor models support multiple variants and details of the variants implemented in this model can be found in:
- the Imperas installation located at ImperasLib/source/mips.ovpworld.org/processor/mips32_r1r5/1.0/doc
- the OVP website: OVP_Model_Specific_Information_mips32_r1r5_4Km.pdf
Description
MIPS32 Configurable Processor Model
Licensing
Usage of binary model under license governing simulator usage. Source of model available under Imperas Software License Agreement.
Limitations
If this model is not part of your installation, then it is available for download from www.OVPworld.org/ip-vendor-mips.
Verification
Models have been validated correct as part of the MIPS Verified program and run through the MIPS AVP test programs
Features
only MIPS32 Instruction set implemented
MMU Type: Fixed Mapping
L1 I and D cache model in either full or tag-only mode implemented (disabled by default)
Instance Parameters
Several parameters can be specified when a processor is instanced in a platform. For this processor instance 'cpu1' it has been instanced with the following parameters:
Table 6: Processor Instance 'cpu1' Parameters (Configurations)
Parameter | Value | Description |
---|
endian | big | Select processor endian (big or little) |
mips | 100 | The nominal MIPS for the processor |
semihostvendor | mips.ovpworld.org | The VLNV vendor name of a Semihost library |
semihostname | mips32Newlib | The VLNV name of a Semihost library |
Table 7: Processor Instance 'cpu1' Parameters (Attributes)
Parameter Name | Value | Type |
---|
variant | 4Km | enum |
Memory Map for processor 'cpu1' bus: 'bus1'
Processor instance 'cpu1' is connected to bus 'bus1' using master port 'INSTRUCTION'.
Processor instance 'cpu1' is connected to bus 'bus1' using master port 'DATA'.
Table 8: Memory Map ( 'cpu1' / 'bus1' [width: 32] )
Lo Address | Hi Address | Instance | Component |
---|
0x0 | 0xFFFFFFFF | memory1 | ram |
Net Connections to processor: 'cpu1'
There are no nets connected to this processor.