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MipsI6500

Model Information


This page provides detailed information about the OVP Fast Processor Model of the MIPS I6500 core.
Processor IP owner is MIPS. More information is available from them here.

OVP Fast Processor Model is written in C.
Provides a C API for use in C based platforms.
Provides a native C++ interface for use in SystemC TLM2 platforms.

The model is written using the OVP VMI API that provides a Virtual Machine Interface that defines the behavior of the processor.
The VMI API makes a clear line between model and simulator allowing very good optimization and world class high speed performance.

The model is provided as a binary shared object and is also available as source (different models have different licensing conditions). This allows the download and use of the model binary or the use of the source to explore and modify the model.

The model has been run through an extensive QA and regression testing process.

Parallel Simulation using Imperas QuantumLeap


Traditionally, processor models and simulators make use of one thread on the host PC. Imperas have developed a technology, called QuantumLeap, that makes use of the many host cores found in modern PC/workstations to achieve industry leading simulation performance. To find out about the Imperas parallel simulation lookup Imperas QuantumLeap. There are videos of QuantumLeap on ARM here, and MIPS here. For press information related to QuantumLeap for ARM click here or for MIPS click here.
Many of the OVP Fast Processor Models have been qualified to work with QuantumLeap - this is indicated for this model below.

Embedded Software Development tools


This model executes instructions of the target architecture and provides an interface for debug access. An interface to GDB is provided and this allows the connection of many industry standard debuggers that use the GDB/RSP interface. For more information watch the OVP video here.
The model also works with the Imperas Multicore Debugger and advanced Verification, Analysis and Profiling tools.

Instruction Set Simulator (ISS) for MIPS I6500


An ISS is a software development tool that takes in instructions for a target processor and executes them. The heart of an ISS is the model of the processor. Imperas has developed a range of ISS products for use in embedded software development that utilize this fast Fast Processor Model. The Imperas MIPS I6500 ISS runs on Windows/Linux x86 systems and takes a cross compiled elf file of your program and allows very fast execution. The MIPS I6500 ISS also provides access to standard GDB/RSP debuggers and connects to the Eclipse IDE and Imperas debuggers.

Overview of MIPS I6500 Fast Processor Model


Model Variant name: I6500
Description:
    MIPS64 Configurable Processor Model
    If you need other variants, these models can be obtained from www.OVPworld.org/MIPSuser.
Licensing:
    Usage of binary model under license governing simulator usage. Source of model available under Imperas Software License Agreement.
Limitations:
    If this model is not part of your installation, then it is available for download from www.OVPworld.org/MIPSuser.
    Cache model does not implement coherency
Verification:
    Models have been validated correct as part of the MIPS Verified program and run through the MIPS AVP test programs
Features:
    Only MIPS64 Instruction set implemented
    MMU Type: Dual VTLB and FTLB
    FPU implemented
    L1 I and D cache model in either full or tag-only mode implemented (disabled by default)
    Vectored interrupts implemented

Model downloadable (needs registration and to be logged in) in package mips64.model for Windows32 and for Linux32
OVP simulator downloadable (needs registration and to be logged in) in package OVPsim for Windows32 and for Linux32
OVP Download page here.
OVP documentation that provides overview information on processor models is available OVP_Guide_To_Using_Processor_Models.pdf.

Full model specific documentation on the variant I6500 is available OVP_Model_Specific_Information_mips64_I6500.pdf.

Configuration


Location: The Fast Processor Model source and object file is found in the installation VLNV tree: mips.ovpworld.org/processor/mips64/1.0
Processor Endian-ness: This model can be set to either endian-ness (normally by a pin, or the ELF code).
Processor ELF Code: The ELF code for this model is: 0x8
QuantumLeap Support: The processor model is qualified to run in a QuantumLeap enabled simulator.

TLM Initiator Ports (Bus Ports)

Port TypeNameWidth (bits)Description
masterINSTRUCTION12
masterDATA12
masterDSPRAM_CPU032
masterDSPRAM_CPU132
masterDSPRAM_CPU232
masterDSPRAM_CPU332

SystemC Signal Ports (Net Ports)

Port TypeNameDescription
resetinput
dintinput
int0input
int1input
int2input
int3input
int4input
int5input
int6input
int7input
int8input
int9input
int10input
int11input
int12input
int13input
int14input
int15input
int16input
int17input
int18input
int19input
int20input
int21input
int22input
int23input
int24input
int25input
int26input
int27input
int28input
int29input
int30input
int31input
int32input
int33input
int34input
int35input
int36input
int37input
int38input
int39input
int40input
int41input
int42input
int43input
int44input
int45input
int46input
int47input
int48input
int49input
int50input
int51input
int52input
int53input
int54input
int55input
int56input
int57input
int58input
int59input
int60input
int61input
int62input
int63input
int64input
int65input
int66input
int67input
int68input
int69input
int70input
int71input
int72input
int73input
int74input
int75input
int76input
int77input
int78input
int79input
int80input
int81input
int82input
int83input
int84input
int85input
int86input
int87input
int88input
int89input
int90input
int91input
int92input
int93input
int94input
int95input
int96input
int97input
int98input
int99input
int100input
int101input
int102input
int103input
int104input
int105input
int106input
int107input
int108input
int109input
int110input
int111input
int112input
int113input
int114input
int115input
int116input
int117input
int118input
int119input
int120input
int121input
int122input
int123input
int124input
int125input
int126input
int127input
ej_disable_probe_debuginput
ejtagbrk_overrideinput
ej_dint_ininput
GCR_CUSTOM_BASEoutput
GCR_CUSTOM_BASE_UPPERoutput
dint_CPU0_VP0input
hwint0_CPU0_VP0input
hwint1_CPU0_VP0input
hwint2_CPU0_VP0input
hwint3_CPU0_VP0input
hwint4_CPU0_VP0input
hwint5_CPU0_VP0input
nmi_CPU0_VP0input
EICPresent_CPU0_VP0input
EIC_RIPL_CPU0_VP0input
EIC_EICSS_CPU0_VP0input
EIC_VectorNum_CPU0_VP0input
EIC_VectorOffset_CPU0_VP0input
EIC_GID_CPU0_VP0input
intISS_CPU0_VP0output
causeTI_CPU0_VP0output
causeIP0_CPU0_VP0output
causeIP1_CPU0_VP0output
si_sleep_CPU0_VP0output
hwint0input
vc_run_CPU0_VP0input
Guest.EIC_RIPL_CPU0_VP0input
Guest.EIC_EICSS_CPU0_VP0input
Guest.EIC_VectorNum_CPU0_VP0input
Guest.EIC_VectorOffset_CPU0_VP0input
Guest.EIC_GID_CPU0_VP0input
Guest.intISS_CPU0_VP0output
Guest.causeTI_CPU0_VP0output
Guest.causeIP0_CPU0_VP0output
Guest.causeIP1_CPU0_VP0output
dint_CPU0_VP1input
hwint0_CPU0_VP1input
hwint1_CPU0_VP1input
hwint2_CPU0_VP1input
hwint3_CPU0_VP1input
hwint4_CPU0_VP1input
hwint5_CPU0_VP1input
nmi_CPU0_VP1input
EICPresent_CPU0_VP1input
EIC_RIPL_CPU0_VP1input
EIC_EICSS_CPU0_VP1input
EIC_VectorNum_CPU0_VP1input
EIC_VectorOffset_CPU0_VP1input
EIC_GID_CPU0_VP1input
intISS_CPU0_VP1output
causeTI_CPU0_VP1output
causeIP0_CPU0_VP1output
causeIP1_CPU0_VP1output
si_sleep_CPU0_VP1output
vc_run_CPU0_VP1input
Guest.EIC_RIPL_CPU0_VP1input
Guest.EIC_EICSS_CPU0_VP1input
Guest.EIC_VectorNum_CPU0_VP1input
Guest.EIC_VectorOffset_CPU0_VP1input
Guest.EIC_GID_CPU0_VP1input
Guest.intISS_CPU0_VP1output
Guest.causeTI_CPU0_VP1output
Guest.causeIP0_CPU0_VP1output
Guest.causeIP1_CPU0_VP1output
dint_CPU1_VP0input
hwint0_CPU1_VP0input
hwint1_CPU1_VP0input
hwint2_CPU1_VP0input
hwint3_CPU1_VP0input
hwint4_CPU1_VP0input
hwint5_CPU1_VP0input
nmi_CPU1_VP0input
EICPresent_CPU1_VP0input
EIC_RIPL_CPU1_VP0input
EIC_EICSS_CPU1_VP0input
EIC_VectorNum_CPU1_VP0input
EIC_VectorOffset_CPU1_VP0input
EIC_GID_CPU1_VP0input
intISS_CPU1_VP0output
causeTI_CPU1_VP0output
causeIP0_CPU1_VP0output
causeIP1_CPU1_VP0output
si_sleep_CPU1_VP0output
vc_run_CPU1_VP0input
Guest.EIC_RIPL_CPU1_VP0input
Guest.EIC_EICSS_CPU1_VP0input
Guest.EIC_VectorNum_CPU1_VP0input
Guest.EIC_VectorOffset_CPU1_VP0input
Guest.EIC_GID_CPU1_VP0input
Guest.intISS_CPU1_VP0output
Guest.causeTI_CPU1_VP0output
Guest.causeIP0_CPU1_VP0output
Guest.causeIP1_CPU1_VP0output
dint_CPU1_VP1input
hwint0_CPU1_VP1input
hwint1_CPU1_VP1input
hwint2_CPU1_VP1input
hwint3_CPU1_VP1input
hwint4_CPU1_VP1input
hwint5_CPU1_VP1input
nmi_CPU1_VP1input
EICPresent_CPU1_VP1input
EIC_RIPL_CPU1_VP1input
EIC_EICSS_CPU1_VP1input
EIC_VectorNum_CPU1_VP1input
EIC_VectorOffset_CPU1_VP1input
EIC_GID_CPU1_VP1input
intISS_CPU1_VP1output
causeTI_CPU1_VP1output
causeIP0_CPU1_VP1output
causeIP1_CPU1_VP1output
si_sleep_CPU1_VP1output
vc_run_CPU1_VP1input
Guest.EIC_RIPL_CPU1_VP1input
Guest.EIC_EICSS_CPU1_VP1input
Guest.EIC_VectorNum_CPU1_VP1input
Guest.EIC_VectorOffset_CPU1_VP1input
Guest.EIC_GID_CPU1_VP1input
Guest.intISS_CPU1_VP1output
Guest.causeTI_CPU1_VP1output
Guest.causeIP0_CPU1_VP1output
Guest.causeIP1_CPU1_VP1output
dint_CPU2_VP0input
hwint0_CPU2_VP0input
hwint1_CPU2_VP0input
hwint2_CPU2_VP0input
hwint3_CPU2_VP0input
hwint4_CPU2_VP0input
hwint5_CPU2_VP0input
nmi_CPU2_VP0input
EICPresent_CPU2_VP0input
EIC_RIPL_CPU2_VP0input
EIC_EICSS_CPU2_VP0input
EIC_VectorNum_CPU2_VP0input
EIC_VectorOffset_CPU2_VP0input
EIC_GID_CPU2_VP0input
intISS_CPU2_VP0output
causeTI_CPU2_VP0output
causeIP0_CPU2_VP0output
causeIP1_CPU2_VP0output
si_sleep_CPU2_VP0output
vc_run_CPU2_VP0input
Guest.EIC_RIPL_CPU2_VP0input
Guest.EIC_EICSS_CPU2_VP0input
Guest.EIC_VectorNum_CPU2_VP0input
Guest.EIC_VectorOffset_CPU2_VP0input
Guest.EIC_GID_CPU2_VP0input
Guest.intISS_CPU2_VP0output
Guest.causeTI_CPU2_VP0output
Guest.causeIP0_CPU2_VP0output
Guest.causeIP1_CPU2_VP0output
dint_CPU2_VP1input
hwint0_CPU2_VP1input
hwint1_CPU2_VP1input
hwint2_CPU2_VP1input
hwint3_CPU2_VP1input
hwint4_CPU2_VP1input
hwint5_CPU2_VP1input
nmi_CPU2_VP1input
EICPresent_CPU2_VP1input
EIC_RIPL_CPU2_VP1input
EIC_EICSS_CPU2_VP1input
EIC_VectorNum_CPU2_VP1input
EIC_VectorOffset_CPU2_VP1input
EIC_GID_CPU2_VP1input
intISS_CPU2_VP1output
causeTI_CPU2_VP1output
causeIP0_CPU2_VP1output
causeIP1_CPU2_VP1output
si_sleep_CPU2_VP1output
vc_run_CPU2_VP1input
Guest.EIC_RIPL_CPU2_VP1input
Guest.EIC_EICSS_CPU2_VP1input
Guest.EIC_VectorNum_CPU2_VP1input
Guest.EIC_VectorOffset_CPU2_VP1input
Guest.EIC_GID_CPU2_VP1input
Guest.intISS_CPU2_VP1output
Guest.causeTI_CPU2_VP1output
Guest.causeIP0_CPU2_VP1output
Guest.causeIP1_CPU2_VP1output
dint_CPU3_VP0input
hwint0_CPU3_VP0input
hwint1_CPU3_VP0input
hwint2_CPU3_VP0input
hwint3_CPU3_VP0input
hwint4_CPU3_VP0input
hwint5_CPU3_VP0input
nmi_CPU3_VP0input
EICPresent_CPU3_VP0input
EIC_RIPL_CPU3_VP0input
EIC_EICSS_CPU3_VP0input
EIC_VectorNum_CPU3_VP0input
EIC_VectorOffset_CPU3_VP0input
EIC_GID_CPU3_VP0input
intISS_CPU3_VP0output
causeTI_CPU3_VP0output
causeIP0_CPU3_VP0output
causeIP1_CPU3_VP0output
si_sleep_CPU3_VP0output
vc_run_CPU3_VP0input
Guest.EIC_RIPL_CPU3_VP0input
Guest.EIC_EICSS_CPU3_VP0input
Guest.EIC_VectorNum_CPU3_VP0input
Guest.EIC_VectorOffset_CPU3_VP0input
Guest.EIC_GID_CPU3_VP0input
Guest.intISS_CPU3_VP0output
Guest.causeTI_CPU3_VP0output
Guest.causeIP0_CPU3_VP0output
Guest.causeIP1_CPU3_VP0output
dint_CPU3_VP1input
hwint0_CPU3_VP1input
hwint1_CPU3_VP1input
hwint2_CPU3_VP1input
hwint3_CPU3_VP1input
hwint4_CPU3_VP1input
hwint5_CPU3_VP1input
nmi_CPU3_VP1input
EICPresent_CPU3_VP1input
EIC_RIPL_CPU3_VP1input
EIC_EICSS_CPU3_VP1input
EIC_VectorNum_CPU3_VP1input
EIC_VectorOffset_CPU3_VP1input
EIC_GID_CPU3_VP1input
intISS_CPU3_VP1output
causeTI_CPU3_VP1output
causeIP0_CPU3_VP1output
causeIP1_CPU3_VP1output
si_sleep_CPU3_VP1output
vc_run_CPU3_VP1input
Guest.EIC_RIPL_CPU3_VP1input
Guest.EIC_EICSS_CPU3_VP1input
Guest.EIC_VectorNum_CPU3_VP1input
Guest.EIC_VectorOffset_CPU3_VP1input
Guest.EIC_GID_CPU3_VP1input
Guest.intISS_CPU3_VP1output
Guest.causeTI_CPU3_VP1output
Guest.causeIP0_CPU3_VP1output
Guest.causeIP1_CPU3_VP1output

No FIFO Ports in I6500.


Exceptions

NameCodeDescription
Int0
Mod1
TLBL2
TLBS3
AdEL4
AdES5
IBE6
DBE7
Sys8
Bp9
RI10
CpU11
Ov12
Tr13
MSAFPE14
FPE15
Impl116
Impl217
C2E18
TLBRI19
TLBXI20
MSADis21
MDMX22
WATCH23
MCheck24
Thread25
DSPDis26
GE27
Prot29
CacheErr30

Execution Modes

ModeCodeDescription
KERNEL0
DEBUG1
SUPERVISOR2
USER3
GUEST_KERNEL4
GUEST_SUPERVISOR5
GUEST_USER6

More Detailed Information

The I6500 OVP Fast Processor Model also has parameters, model commands, and many registers.
The model may also have hierarchy or be multicore and have other attributes and capabilities.
To see this information, please have a look at the model variant specific documents.
Click here to see the detailed document OVP_Model_Specific_Information_mips64_I6500.pdf.

Other Sites/Pages with similar information

Information on the I6500 OVP Fast Processor Model can also be found on other web sites:
www.imperas.com has more information on the model library.



MipsProcessors
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