OVP Peripheral Model: MipsMaltaFPGA

Model Specific Information

This page provides introductory usage information for an Imperas OVP peripheral behavioral model. The page is split into sections providing specific information for this peripheral, including any ports for connecting into a platform, registers, other component parts, and configuration options and general information for peripheral modeling with Imperas OVP.


Open Source Apache 2.0


MIPS MALTA FPGA. Drives Development board functions.


This model has sufficient functionality to allow a Linux Kernel to Boot on the MIPS:MALTA platform.


MIPS Malta User Manual.


The MaltaFPGA peripheral model is located in an Imperas/OVP installation at the VLNV: / peripheral / MaltaFPGA / 1.0.

Peripheral Instance Parameters

This model accepts the following parameters:

Table : Peripheral Parameters

stoponsoftresetboolIf non:zero, when the software reset register is written the simulation will terminate. By Default the software reset register has no effect.
switchesuns32This value is used to initialise the set on input switches to the Malta FPGA.

Bus Slave Ports

This model has the following bus slave ports:

Bus Slave Port: busPort1

Table 1: Bus Slave Port: busPort1

NameSize (bytes)Must Be ConnectedDescription
busPort10x900F (False)

No address blocks have been defined for this slave port.

Bus Slave Port: busPort2

Table 2: Bus Slave Port: busPort2

NameSize (bytes)Must Be ConnectedDescription
busPort20x600F (False)

No address blocks have been defined for this slave port.

Platforms that use this peripheral component

Peripheral components can be used in many different platforms, including those developed by Imperas or by other users of OVP. You can use this peripheral in your own platforms.

Table 3: Publicly available platforms using peripheral 'MaltaFPGA'

Platform NameVendor

Page was generated in 0.0121 seconds