OVP Peripheral Model: MipsMaltaFPGA
Model Specific Information
This page provides introductory usage information for an Imperas OVP peripheral behavioral model.
The page is split into sections providing specific information for this peripheral,
including any ports for connecting into a platform, registers, other component parts, and configuration options and general information for peripheral modeling with Imperas OVP.
Licensing
Open Source Apache 2.0
Description
MIPS MALTA FPGA. Drives Development board functions.
Limitations
This model has sufficient functionality to allow a Linux Kernel to Boot on the MIPS:MALTA platform.
Reference
MIPS Malta User Manual.
Location
The MaltaFPGA peripheral model is located in an Imperas/OVP installation at the VLNV: mips.ovpworld.org / peripheral / MaltaFPGA / 1.0.
Peripheral Instance Parameters
This model accepts the following parameters:
Table : Peripheral Parameters
Name | Type | Description |
---|
stoponsoftreset | bool | If non:zero, when the software reset register is written the simulation will terminate. By Default the software reset register has no effect. |
switches | uns32 | This value is used to initialise the set on input switches to the Malta FPGA. |
Bus Slave Ports
This model has the following bus slave ports:
Bus Slave Port: busPort1
Table 1: Bus Slave Port: busPort1
Name | Size (bytes) | Must Be Connected | Description |
---|
busPort1 | 0x900 | F (False) | |
No address blocks have been defined for this slave port.
Bus Slave Port: busPort2
Table 2: Bus Slave Port: busPort2
Name | Size (bytes) | Must Be Connected | Description |
---|
busPort2 | 0x600 | F (False) | |
No address blocks have been defined for this slave port.
Platforms that use this peripheral component
Peripheral components can be used in many different platforms, including those developed by Imperas or by other users of OVP. You can use this peripheral in your own platforms.
Table 3: Publicly available platforms using peripheral 'MaltaFPGA'