Port Type | Name | Width (bits) | Description |
---|---|---|---|
master | INSTRUCTION | 12 | |
master | DATA | 12 | |
master | USPRAM | 32 |
This page provides detailed information about the OVP Fast Processor Model of the MIPS P5600 core.
Processor IP owner is MIPS. More information is available from them here.
OVP Fast Processor Model is written in C.
Provides a C API for use in C based platforms.
Provides a native C++ interface for use in SystemC TLM2 platforms.
The model is written using the OVP VMI API that provides a Virtual Machine Interface that defines the behavior of the processor.
The VMI API makes a clear line between model and simulator allowing very good optimization and world class high speed performance.
The model is provided as a binary shared object and is also available as source (different models have different licensing conditions). This allows the download and use of the model binary or the use of the source to explore and modify the model.
The model has been run through an extensive QA and regression testing process.
Port Type | Name | Width (bits) | Description |
---|---|---|---|
master | INSTRUCTION | 12 | |
master | DATA | 12 | |
master | USPRAM | 32 |
Port Type | Name | Description |
---|---|---|
reset | input | |
dint | input | |
int0 | input | |
int1 | input | |
int2 | input | |
int3 | input | |
int4 | input | |
int5 | input | |
int6 | input | |
int7 | input | |
int8 | input | |
int9 | input | |
int10 | input | |
int11 | input | |
int12 | input | |
int13 | input | |
int14 | input | |
int15 | input | |
int16 | input | |
int17 | input | |
int18 | input | |
int19 | input | |
int20 | input | |
int21 | input | |
int22 | input | |
int23 | input | |
int24 | input | |
int25 | input | |
int26 | input | |
int27 | input | |
int28 | input | |
int29 | input | |
int30 | input | |
int31 | input | |
int32 | input | |
int33 | input | |
int34 | input | |
int35 | input | |
int36 | input | |
int37 | input | |
int38 | input | |
int39 | input | |
ej_disable_probe_debug | input | |
ejtagbrk_override | input | |
ej_dint_in | input | |
GCR_CUSTOM_BASE | output | |
GCR_CUSTOM_BASE_UPPER | output | |
reset_CPU0 | input | |
hwint0_CPU0 | input | |
hwint1_CPU0 | input | |
hwint2_CPU0 | input | |
hwint3_CPU0 | input | |
hwint4_CPU0 | input | |
hwint5_CPU0 | input | |
nmi_CPU0 | input | |
EICPresent_CPU0 | input | |
EIC_RIPL_CPU0 | input | |
EIC_EICSS_CPU0 | input | |
EIC_VectorNum_CPU0 | input | |
EIC_VectorOffset_CPU0 | input | |
EIC_GID_CPU0 | input | |
intISS_CPU0 | output | |
causeTI_CPU0 | output | |
causeIP0_CPU0 | output | |
causeIP1_CPU0 | output | |
si_sleep_CPU0 | output | |
hwint0 | input | |
vc_run_CPU0 | input | |
Guest.EIC_RIPL_CPU0 | input | |
Guest.EIC_EICSS_CPU0 | input | |
Guest.EIC_VectorNum_CPU0 | input | |
Guest.EIC_VectorOffset_CPU0 | input | |
Guest.EIC_GID_CPU0 | input | |
Guest.intISS_CPU0 | output | |
Guest.causeTI_CPU0 | output | |
Guest.causeIP0_CPU0 | output | |
Guest.causeIP1_CPU0 | output | |
reset_CPU1 | input | |
hwint0_CPU1 | input | |
hwint1_CPU1 | input | |
hwint2_CPU1 | input | |
hwint3_CPU1 | input | |
hwint4_CPU1 | input | |
hwint5_CPU1 | input | |
nmi_CPU1 | input | |
EICPresent_CPU1 | input | |
EIC_RIPL_CPU1 | input | |
EIC_EICSS_CPU1 | input | |
EIC_VectorNum_CPU1 | input | |
EIC_VectorOffset_CPU1 | input | |
EIC_GID_CPU1 | input | |
intISS_CPU1 | output | |
causeTI_CPU1 | output | |
causeIP0_CPU1 | output | |
causeIP1_CPU1 | output | |
si_sleep_CPU1 | output | |
vc_run_CPU1 | input | |
Guest.EIC_RIPL_CPU1 | input | |
Guest.EIC_EICSS_CPU1 | input | |
Guest.EIC_VectorNum_CPU1 | input | |
Guest.EIC_VectorOffset_CPU1 | input | |
Guest.EIC_GID_CPU1 | input | |
Guest.intISS_CPU1 | output | |
Guest.causeTI_CPU1 | output | |
Guest.causeIP0_CPU1 | output | |
Guest.causeIP1_CPU1 | output | |
reset_CPU2 | input | |
hwint0_CPU2 | input | |
hwint1_CPU2 | input | |
hwint2_CPU2 | input | |
hwint3_CPU2 | input | |
hwint4_CPU2 | input | |
hwint5_CPU2 | input | |
nmi_CPU2 | input | |
EICPresent_CPU2 | input | |
EIC_RIPL_CPU2 | input | |
EIC_EICSS_CPU2 | input | |
EIC_VectorNum_CPU2 | input | |
EIC_VectorOffset_CPU2 | input | |
EIC_GID_CPU2 | input | |
intISS_CPU2 | output | |
causeTI_CPU2 | output | |
causeIP0_CPU2 | output | |
causeIP1_CPU2 | output | |
si_sleep_CPU2 | output | |
vc_run_CPU2 | input | |
Guest.EIC_RIPL_CPU2 | input | |
Guest.EIC_EICSS_CPU2 | input | |
Guest.EIC_VectorNum_CPU2 | input | |
Guest.EIC_VectorOffset_CPU2 | input | |
Guest.EIC_GID_CPU2 | input | |
Guest.intISS_CPU2 | output | |
Guest.causeTI_CPU2 | output | |
Guest.causeIP0_CPU2 | output | |
Guest.causeIP1_CPU2 | output | |
reset_CPU3 | input | |
hwint0_CPU3 | input | |
hwint1_CPU3 | input | |
hwint2_CPU3 | input | |
hwint3_CPU3 | input | |
hwint4_CPU3 | input | |
hwint5_CPU3 | input | |
nmi_CPU3 | input | |
EICPresent_CPU3 | input | |
EIC_RIPL_CPU3 | input | |
EIC_EICSS_CPU3 | input | |
EIC_VectorNum_CPU3 | input | |
EIC_VectorOffset_CPU3 | input | |
EIC_GID_CPU3 | input | |
intISS_CPU3 | output | |
causeTI_CPU3 | output | |
causeIP0_CPU3 | output | |
causeIP1_CPU3 | output | |
si_sleep_CPU3 | output | |
vc_run_CPU3 | input | |
Guest.EIC_RIPL_CPU3 | input | |
Guest.EIC_EICSS_CPU3 | input | |
Guest.EIC_VectorNum_CPU3 | input | |
Guest.EIC_VectorOffset_CPU3 | input | |
Guest.EIC_GID_CPU3 | input | |
Guest.intISS_CPU3 | output | |
Guest.causeTI_CPU3 | output | |
Guest.causeIP0_CPU3 | output | |
Guest.causeIP1_CPU3 | output |
Name | Code | Description |
---|---|---|
Int | 0 | |
Mod | 1 | |
TLBL | 2 | |
TLBS | 3 | |
AdEL | 4 | |
AdES | 5 | |
IBE | 6 | |
DBE | 7 | |
Sys | 8 | |
Bp | 9 | |
RI | 10 | |
CpU | 11 | |
Ov | 12 | |
Tr | 13 | |
MSAFPE | 14 | |
FPE | 15 | |
Impl1 | 16 | |
Impl2 | 17 | |
C2E | 18 | |
TLBRI | 19 | |
TLBXI | 20 | |
MSADis | 21 | |
MDMX | 22 | |
WATCH | 23 | |
MCheck | 24 | |
Thread | 25 | |
DSPDis | 26 | |
GE | 27 | |
Prot | 29 | |
CacheErr | 30 |
Mode | Code | Description |
---|---|---|
KERNEL | 0 | |
DEBUG | 1 | |
SUPERVISOR | 2 | |
USER | 3 | |
GUEST_KERNEL | 4 | |
GUEST_SUPERVISOR | 5 | |
GUEST_USER | 6 |
The P5600 OVP Fast Processor Model also has parameters, model commands, and many registers.
The model may also have hierarchy or be multicore and have other attributes and capabilities.
To see this information, please have a look at the model variant specific documents.
Click here to see the detailed document OVP_Model_Specific_Information_mips32_P5600.pdf.
Information on the P5600 OVP Fast Processor Model can also be found on other web sites:
www.imperas.com has more information on the model library.