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MipsP6600

Model Information


This page provides detailed information about the OVP Fast Processor Model of the MIPS P6600 core.
Processor IP owner is MIPS. More information is available from them here.

OVP Fast Processor Model is written in C.
Provides a C API for use in C based platforms.
Provides a native C++ interface for use in SystemC TLM2 platforms.

The model is written using the OVP VMI API that provides a Virtual Machine Interface that defines the behavior of the processor.
The VMI API makes a clear line between model and simulator allowing very good optimization and world class high speed performance.

The model is provided as a binary shared object and is also available as source (different models have different licensing conditions). This allows the download and use of the model binary or the use of the source to explore and modify the model.

The model has been run through an extensive QA and regression testing process.

Parallel Simulation using Imperas QuantumLeap


Traditionally, processor models and simulators make use of one thread on the host PC. Imperas have developed a technology, called QuantumLeap, that makes use of the many host cores found in modern PC/workstations to achieve industry leading simulation performance. To find out about the Imperas parallel simulation lookup Imperas QuantumLeap. There are videos of QuantumLeap on ARM here, and MIPS here. For press information related to QuantumLeap for ARM click here or for MIPS click here.
Many of the OVP Fast Processor Models have been qualified to work with QuantumLeap - this is indicated for this model below.

Embedded Software Development tools


This model executes instructions of the target architecture and provides an interface for debug access. An interface to GDB is provided and this allows the connection of many industry standard debuggers that use the GDB/RSP interface. For more information watch the OVP video here.
The model also works with the Imperas Multicore Debugger and advanced Verification, Analysis and Profiling tools.

Instruction Set Simulator (ISS) for MIPS P6600


An ISS is a software development tool that takes in instructions for a target processor and executes them. The heart of an ISS is the model of the processor. Imperas has developed a range of ISS products for use in embedded software development that utilize this fast Fast Processor Model. The Imperas MIPS P6600 ISS runs on Windows/Linux x86 systems and takes a cross compiled elf file of your program and allows very fast execution. The MIPS P6600 ISS also provides access to standard GDB/RSP debuggers and connects to the Eclipse IDE and Imperas debuggers.

Overview of MIPS P6600 Fast Processor Model


Model Variant name: P6600
Description:
    MIPS64 Configurable Processor Model
    If you need other variants, these models can be obtained from www.OVPworld.org/MIPSuser.
Licensing:
    Usage of binary model under license governing simulator usage. Source of model available under Imperas Software License Agreement.
Limitations:
    If this model is not part of your installation, then it is available for download from www.OVPworld.org/MIPSuser.
    Cache model does not implement coherency
Verification:
    Models have been validated correct as part of the MIPS Verified program and run through the MIPS AVP test programs
Features:
    Only MIPS64 Instruction set implemented
    MMU Type: Standard TLB
    FPU implemented
    L1 I and D cache model in either full or tag-only mode implemented (disabled by default)
    Segmentation control implemented
    Enhanced virtual address (EVA) supported
    Vectored interrupts implemented

Model downloadable (needs registration and to be logged in) in package mips64.model for Windows32 and for Linux32
OVP simulator downloadable (needs registration and to be logged in) in package OVPsim for Windows32 and for Linux32
OVP Download page here.
OVP documentation that provides overview information on processor models is available OVP_Guide_To_Using_Processor_Models.pdf.

Full model specific documentation on the variant P6600 is available OVP_Model_Specific_Information_mips64_P6600.pdf.

Configuration


Location: The Fast Processor Model source and object file is found in the installation VLNV tree: mips.ovpworld.org/processor/mips64/1.0
Processor Endian-ness: This model can be set to either endian-ness (normally by a pin, or the ELF code).
Processor ELF Code: The ELF code for this model is: 0x8
QuantumLeap Support: The processor model is qualified to run in a QuantumLeap enabled simulator.

TLM Initiator Ports (Bus Ports)

Port TypeNameWidth (bits)Description
masterINSTRUCTION12
masterDATA12
masterUSPRAM32

SystemC Signal Ports (Net Ports)

Port TypeNameDescription
resetinput
dintinput
int0input
int1input
int2input
int3input
int4input
int5input
int6input
int7input
int8input
int9input
int10input
int11input
int12input
int13input
int14input
int15input
int16input
int17input
int18input
int19input
int20input
int21input
int22input
int23input
int24input
int25input
int26input
int27input
int28input
int29input
int30input
int31input
int32input
int33input
int34input
int35input
int36input
int37input
int38input
int39input
ej_disable_probe_debuginput
ejtagbrk_overrideinput
ej_dint_ininput
GCR_CUSTOM_BASEoutput
GCR_CUSTOM_BASE_UPPERoutput
reset_CPU0input
hwint0_CPU0input
hwint1_CPU0input
hwint2_CPU0input
hwint3_CPU0input
hwint4_CPU0input
hwint5_CPU0input
nmi_CPU0input
EICPresent_CPU0input
EIC_RIPL_CPU0input
EIC_EICSS_CPU0input
EIC_VectorNum_CPU0input
EIC_VectorOffset_CPU0input
EIC_GID_CPU0input
intISS_CPU0output
causeTI_CPU0output
causeIP0_CPU0output
causeIP1_CPU0output
si_sleep_CPU0output
hwint0input
vc_run_CPU0input
Guest.EIC_RIPL_CPU0input
Guest.EIC_EICSS_CPU0input
Guest.EIC_VectorNum_CPU0input
Guest.EIC_VectorOffset_CPU0input
Guest.EIC_GID_CPU0input
Guest.intISS_CPU0output
Guest.causeTI_CPU0output
Guest.causeIP0_CPU0output
Guest.causeIP1_CPU0output
reset_CPU1input
hwint0_CPU1input
hwint1_CPU1input
hwint2_CPU1input
hwint3_CPU1input
hwint4_CPU1input
hwint5_CPU1input
nmi_CPU1input
EICPresent_CPU1input
EIC_RIPL_CPU1input
EIC_EICSS_CPU1input
EIC_VectorNum_CPU1input
EIC_VectorOffset_CPU1input
EIC_GID_CPU1input
intISS_CPU1output
causeTI_CPU1output
causeIP0_CPU1output
causeIP1_CPU1output
si_sleep_CPU1output
vc_run_CPU1input
Guest.EIC_RIPL_CPU1input
Guest.EIC_EICSS_CPU1input
Guest.EIC_VectorNum_CPU1input
Guest.EIC_VectorOffset_CPU1input
Guest.EIC_GID_CPU1input
Guest.intISS_CPU1output
Guest.causeTI_CPU1output
Guest.causeIP0_CPU1output
Guest.causeIP1_CPU1output
reset_CPU2input
hwint0_CPU2input
hwint1_CPU2input
hwint2_CPU2input
hwint3_CPU2input
hwint4_CPU2input
hwint5_CPU2input
nmi_CPU2input
EICPresent_CPU2input
EIC_RIPL_CPU2input
EIC_EICSS_CPU2input
EIC_VectorNum_CPU2input
EIC_VectorOffset_CPU2input
EIC_GID_CPU2input
intISS_CPU2output
causeTI_CPU2output
causeIP0_CPU2output
causeIP1_CPU2output
si_sleep_CPU2output
vc_run_CPU2input
Guest.EIC_RIPL_CPU2input
Guest.EIC_EICSS_CPU2input
Guest.EIC_VectorNum_CPU2input
Guest.EIC_VectorOffset_CPU2input
Guest.EIC_GID_CPU2input
Guest.intISS_CPU2output
Guest.causeTI_CPU2output
Guest.causeIP0_CPU2output
Guest.causeIP1_CPU2output
reset_CPU3input
hwint0_CPU3input
hwint1_CPU3input
hwint2_CPU3input
hwint3_CPU3input
hwint4_CPU3input
hwint5_CPU3input
nmi_CPU3input
EICPresent_CPU3input
EIC_RIPL_CPU3input
EIC_EICSS_CPU3input
EIC_VectorNum_CPU3input
EIC_VectorOffset_CPU3input
EIC_GID_CPU3input
intISS_CPU3output
causeTI_CPU3output
causeIP0_CPU3output
causeIP1_CPU3output
si_sleep_CPU3output
vc_run_CPU3input
Guest.EIC_RIPL_CPU3input
Guest.EIC_EICSS_CPU3input
Guest.EIC_VectorNum_CPU3input
Guest.EIC_VectorOffset_CPU3input
Guest.EIC_GID_CPU3input
Guest.intISS_CPU3output
Guest.causeTI_CPU3output
Guest.causeIP0_CPU3output
Guest.causeIP1_CPU3output

No FIFO Ports in P6600.


Exceptions

NameCodeDescription
Int0
Mod1
TLBL2
TLBS3
AdEL4
AdES5
IBE6
DBE7
Sys8
Bp9
RI10
CpU11
Ov12
Tr13
MSAFPE14
FPE15
Impl116
Impl217
C2E18
TLBRI19
TLBXI20
MSADis21
MDMX22
WATCH23
MCheck24
Thread25
DSPDis26
GE27
Prot29
CacheErr30

Execution Modes

ModeCodeDescription
KERNEL0
DEBUG1
SUPERVISOR2
USER3
GUEST_KERNEL4
GUEST_SUPERVISOR5
GUEST_USER6

More Detailed Information

The P6600 OVP Fast Processor Model also has parameters, model commands, and many registers.
The model may also have hierarchy or be multicore and have other attributes and capabilities.
To see this information, please have a look at the model variant specific documents.
Click here to see the detailed document OVP_Model_Specific_Information_mips64_P6600.pdf.

Other Sites/Pages with similar information

Information on the P6600 OVP Fast Processor Model can also be found on other web sites:
www.imperas.com has more information on the model library.



MipsProcessors
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