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MultiCluster

Model Information


This page provides detailed information about the OVP Fast Processor Model of the ARM MultiCluster core.
Processor IP owner is ARM Holdings. More information is available from them here.

OVP Fast Processor Model is written in C.
Provides a C API for use in C based platforms.
Provides a native C++ interface for use in SystemC TLM2 platforms.

The model is written using the OVP VMI API that provides a Virtual Machine Interface that defines the behavior of the processor.
The VMI API makes a clear line between model and simulator allowing very good optimization and world class high speed performance.

The model is provided as a binary shared object and is also available as source (different models have different licensing conditions). This allows the download and use of the model binary or the use of the source to explore and modify the model.

The model has been run through an extensive QA and regression testing process.

Parallel Simulation using Imperas QuantumLeap


Traditionally, processor models and simulators make use of one thread on the host PC. Imperas have developed a technology, called QuantumLeap, that makes use of the many host cores found in modern PC/workstations to achieve industry leading simulation performance. To find out about the Imperas parallel simulation lookup Imperas QuantumLeap. There are videos of QuantumLeap on ARM here, and MIPS here. For press information related to QuantumLeap for ARM click here or for MIPS click here.
Many of the OVP Fast Processor Models have been qualified to work with QuantumLeap - this is indicated for this model below.

Embedded Software Development tools


This model executes instructions of the target architecture and provides an interface for debug access. An interface to GDB is provided and this allows the connection of many industry standard debuggers that use the GDB/RSP interface. For more information watch the OVP video here.
The model also works with the Imperas Multicore Debugger and advanced Verification, Analysis and Profiling tools.

Instruction Set Simulator (ISS) for ARM MultiCluster


An ISS is a software development tool that takes in instructions for a target processor and executes them. The heart of an ISS is the model of the processor. Imperas has developed a range of ISS products for use in embedded software development that utilize this fast Fast Processor Model. The Imperas ARM MultiCluster ISS runs on Windows/Linux x86 systems and takes a cross compiled elf file of your program and allows very fast execution. The ARM MultiCluster ISS also provides access to standard GDB/RSP debuggers and connects to the Eclipse IDE and Imperas debuggers.

Overview of ARM MultiCluster Fast Processor Model


Model Variant name: MultiCluster
Description:
    This model implements an ARM system containing clusters of MPCore processors communicating using a common GICv2 or GICv3 block.
    By default, the system contains Cortex-A53MPx4 and Cortex-A57MPx4 clusters, but this can be changed using parameter "override_clusterVariants". This parameter is a comma-separated list of cluster components (e.g. "Cortex-A53MPx4,Cortex-A57MPx4"). Note that if a GICv2 is selected, the total number of PEs must not exceed 8.
Licensing:
    This document describes the interface to the MultiCluster only. Refer to documentation of individual clusters for information regarding implemented features, licensing and limitations.
Features:
    By default, the model implements a GICv2. Parameter enableGICv3 can be used to select a GICv3 instead.

Model downloadable (needs registration and to be logged in) in package arm.model for Windows32 and for Linux32
OVP simulator downloadable (needs registration and to be logged in) in package OVPsim for Windows32 and for Linux32
OVP Download page here.
OVP documentation that provides overview information on processor models is available OVP_Guide_To_Using_Processor_Models.pdf.

Full model specific documentation on the variant MultiCluster is available OVP_Model_Specific_Information_arm_MultiCluster.pdf.

Configuration


Location: The Fast Processor Model source and object file is found in the installation VLNV tree: arm.ovpworld.org/processor/arm/1.0
Processor Endian-ness: This model can be set to either endian-ness (normally by a pin, or the ELF code).
Processor ELF Code: The ELF code for this model is: 0xb7
QuantumLeap Support: The processor model is qualified to run in a QuantumLeap enabled simulator.

TLM Initiator Ports (Bus Ports)

Port TypeNameWidth (bits)Description
masterINSTRUCTION32
masterDATA32
masterGICRegisters32

SystemC Signal Ports (Net Ports)

Port TypeNameDescription
SPI32input
SPI33input
SPI34input
SPI35input
SPI36input
SPI37input
SPI38input
SPI39input
SPI40input
SPI41input
SPI42input
SPI43input
SPI44input
SPI45input
SPI46input
SPI47input
SPI48input
SPI49input
SPI50input
SPI51input
SPI52input
SPI53input
SPI54input
SPI55input
SPI56input
SPI57input
SPI58input
SPI59input
SPI60input
SPI61input
SPI62input
SPI63input
SPI64input
SPI65input
SPI66input
SPI67input
SPI68input
SPI69input
SPI70input
SPI71input
SPI72input
SPI73input
SPI74input
SPI75input
SPI76input
SPI77input
SPI78input
SPI79input
SPI80input
SPI81input
SPI82input
SPI83input
SPI84input
SPI85input
SPI86input
SPI87input
SPI88input
SPI89input
SPI90input
SPI91input
SPI92input
SPI93input
SPI94input
SPI95input
SPIVectorinput
periphResetinput
CFGSDISABLEinput
GICCDISABLEinput
EVENTIinput
EVENTOoutput
PPI16_C0_0input
PPI17_C0_0input
PPI18_C0_0input
PPI19_C0_0input
PPI20_C0_0input
PPI21_C0_0input
PPI22_C0_0input
PPI23_C0_0input
PPI24_C0_0input
PPI25_C0_0input
PPI26_C0_0input
PPI27_C0_0input
PPI28_C0_0input
PPI29_C0_0input
PPI30_C0_0input
PPI31_C0_0input
CNTVIRQ_C0_0output
CNTPSIRQ_C0_0output
CNTPNSIRQ_C0_0output
CNTPHPIRQ_C0_0output
IRQOUT_C0_0output
FIQOUT_C0_0output
CLUSTERIDAFF1_C0input
CLUSTERIDAFF2_C0input
CLUSTERIDAFF3_C0input
RVBARADDRx_C0_0input
AA64nAA32_C0_0input
VINITHI_C0_0input
CFGEND_C0_0input
CFGTE_C0_0input
reset_C0_0input
fiq_C0_0input
irq_C0_0input
sei_C0_0input
vfiq_C0_0input
virq_C0_0input
vsei_C0_0input
AXI_SLVERR_C0_0input
CP15SDISABLE_C0_0input
PMUIRQ_C0_0output
SMPEN_C0_0output
PPI16_C0_1input
PPI17_C0_1input
PPI18_C0_1input
PPI19_C0_1input
PPI20_C0_1input
PPI21_C0_1input
PPI22_C0_1input
PPI23_C0_1input
PPI24_C0_1input
PPI25_C0_1input
PPI26_C0_1input
PPI27_C0_1input
PPI28_C0_1input
PPI29_C0_1input
PPI30_C0_1input
PPI31_C0_1input
CNTVIRQ_C0_1output
CNTPSIRQ_C0_1output
CNTPNSIRQ_C0_1output
CNTPHPIRQ_C0_1output
IRQOUT_C0_1output
FIQOUT_C0_1output
RVBARADDRx_C0_1input
AA64nAA32_C0_1input
VINITHI_C0_1input
CFGEND_C0_1input
CFGTE_C0_1input
reset_C0_1input
fiq_C0_1input
irq_C0_1input
sei_C0_1input
vfiq_C0_1input
virq_C0_1input
vsei_C0_1input
AXI_SLVERR_C0_1input
CP15SDISABLE_C0_1input
PMUIRQ_C0_1output
SMPEN_C0_1output
PPI16_C0_2input
PPI17_C0_2input
PPI18_C0_2input
PPI19_C0_2input
PPI20_C0_2input
PPI21_C0_2input
PPI22_C0_2input
PPI23_C0_2input
PPI24_C0_2input
PPI25_C0_2input
PPI26_C0_2input
PPI27_C0_2input
PPI28_C0_2input
PPI29_C0_2input
PPI30_C0_2input
PPI31_C0_2input
CNTVIRQ_C0_2output
CNTPSIRQ_C0_2output
CNTPNSIRQ_C0_2output
CNTPHPIRQ_C0_2output
IRQOUT_C0_2output
FIQOUT_C0_2output
RVBARADDRx_C0_2input
AA64nAA32_C0_2input
VINITHI_C0_2input
CFGEND_C0_2input
CFGTE_C0_2input
reset_C0_2input
fiq_C0_2input
irq_C0_2input
sei_C0_2input
vfiq_C0_2input
virq_C0_2input
vsei_C0_2input
AXI_SLVERR_C0_2input
CP15SDISABLE_C0_2input
PMUIRQ_C0_2output
SMPEN_C0_2output
PPI16_C0_3input
PPI17_C0_3input
PPI18_C0_3input
PPI19_C0_3input
PPI20_C0_3input
PPI21_C0_3input
PPI22_C0_3input
PPI23_C0_3input
PPI24_C0_3input
PPI25_C0_3input
PPI26_C0_3input
PPI27_C0_3input
PPI28_C0_3input
PPI29_C0_3input
PPI30_C0_3input
PPI31_C0_3input
CNTVIRQ_C0_3output
CNTPSIRQ_C0_3output
CNTPNSIRQ_C0_3output
CNTPHPIRQ_C0_3output
IRQOUT_C0_3output
FIQOUT_C0_3output
RVBARADDRx_C0_3input
AA64nAA32_C0_3input
VINITHI_C0_3input
CFGEND_C0_3input
CFGTE_C0_3input
reset_C0_3input
fiq_C0_3input
irq_C0_3input
sei_C0_3input
vfiq_C0_3input
virq_C0_3input
vsei_C0_3input
AXI_SLVERR_C0_3input
CP15SDISABLE_C0_3input
PMUIRQ_C0_3output
SMPEN_C0_3output
PPI16_C1_0input
PPI17_C1_0input
PPI18_C1_0input
PPI19_C1_0input
PPI20_C1_0input
PPI21_C1_0input
PPI22_C1_0input
PPI23_C1_0input
PPI24_C1_0input
PPI25_C1_0input
PPI26_C1_0input
PPI27_C1_0input
PPI28_C1_0input
PPI29_C1_0input
PPI30_C1_0input
PPI31_C1_0input
CNTVIRQ_C1_0output
CNTPSIRQ_C1_0output
CNTPNSIRQ_C1_0output
CNTPHPIRQ_C1_0output
IRQOUT_C1_0output
FIQOUT_C1_0output
CLUSTERIDAFF1_C1input
CLUSTERIDAFF2_C1input
CLUSTERIDAFF3_C1input
RVBARADDRx_C1_0input
AA64nAA32_C1_0input
VINITHI_C1_0input
CFGEND_C1_0input
CFGTE_C1_0input
reset_C1_0input
fiq_C1_0input
irq_C1_0input
sei_C1_0input
vfiq_C1_0input
virq_C1_0input
vsei_C1_0input
AXI_SLVERR_C1_0input
CP15SDISABLE_C1_0input
PMUIRQ_C1_0output
SMPEN_C1_0output
PPI16_C1_1input
PPI17_C1_1input
PPI18_C1_1input
PPI19_C1_1input
PPI20_C1_1input
PPI21_C1_1input
PPI22_C1_1input
PPI23_C1_1input
PPI24_C1_1input
PPI25_C1_1input
PPI26_C1_1input
PPI27_C1_1input
PPI28_C1_1input
PPI29_C1_1input
PPI30_C1_1input
PPI31_C1_1input
CNTVIRQ_C1_1output
CNTPSIRQ_C1_1output
CNTPNSIRQ_C1_1output
CNTPHPIRQ_C1_1output
IRQOUT_C1_1output
FIQOUT_C1_1output
RVBARADDRx_C1_1input
AA64nAA32_C1_1input
VINITHI_C1_1input
CFGEND_C1_1input
CFGTE_C1_1input
reset_C1_1input
fiq_C1_1input
irq_C1_1input
sei_C1_1input
vfiq_C1_1input
virq_C1_1input
vsei_C1_1input
AXI_SLVERR_C1_1input
CP15SDISABLE_C1_1input
PMUIRQ_C1_1output
SMPEN_C1_1output
PPI16_C1_2input
PPI17_C1_2input
PPI18_C1_2input
PPI19_C1_2input
PPI20_C1_2input
PPI21_C1_2input
PPI22_C1_2input
PPI23_C1_2input
PPI24_C1_2input
PPI25_C1_2input
PPI26_C1_2input
PPI27_C1_2input
PPI28_C1_2input
PPI29_C1_2input
PPI30_C1_2input
PPI31_C1_2input
CNTVIRQ_C1_2output
CNTPSIRQ_C1_2output
CNTPNSIRQ_C1_2output
CNTPHPIRQ_C1_2output
IRQOUT_C1_2output
FIQOUT_C1_2output
RVBARADDRx_C1_2input
AA64nAA32_C1_2input
VINITHI_C1_2input
CFGEND_C1_2input
CFGTE_C1_2input
reset_C1_2input
fiq_C1_2input
irq_C1_2input
sei_C1_2input
vfiq_C1_2input
virq_C1_2input
vsei_C1_2input
AXI_SLVERR_C1_2input
CP15SDISABLE_C1_2input
PMUIRQ_C1_2output
SMPEN_C1_2output
PPI16_C1_3input
PPI17_C1_3input
PPI18_C1_3input
PPI19_C1_3input
PPI20_C1_3input
PPI21_C1_3input
PPI22_C1_3input
PPI23_C1_3input
PPI24_C1_3input
PPI25_C1_3input
PPI26_C1_3input
PPI27_C1_3input
PPI28_C1_3input
PPI29_C1_3input
PPI30_C1_3input
PPI31_C1_3input
CNTVIRQ_C1_3output
CNTPSIRQ_C1_3output
CNTPNSIRQ_C1_3output
CNTPHPIRQ_C1_3output
IRQOUT_C1_3output
FIQOUT_C1_3output
RVBARADDRx_C1_3input
AA64nAA32_C1_3input
VINITHI_C1_3input
CFGEND_C1_3input
CFGTE_C1_3input
reset_C1_3input
fiq_C1_3input
irq_C1_3input
sei_C1_3input
vfiq_C1_3input
virq_C1_3input
vsei_C1_3input
AXI_SLVERR_C1_3input
CP15SDISABLE_C1_3input
PMUIRQ_C1_3output
SMPEN_C1_3output

No FIFO Ports in MultiCluster.


Exceptions

NameCodeDescription
Reset0
Undefined1
SupervisorCall2
SecureMonitorCall3
HypervisorCall4
PrefetchAbort5
DataAbort6
HypervisorTrap7
IRQ8
FIQ9
IllegalState10
MisalignedPC11
MisalignedSP12
SError13

Execution Modes

ModeCodeDescription
EL0t0
EL1t4
EL1h5
EL2t8
EL2h9
EL3t12
EL3h13
User16
FIQ17
IRQ18
Supervisor19
Monitor22
Abort23
Hypervisor26
Undefined27
System31

More Detailed Information

The MultiCluster OVP Fast Processor Model also has parameters, model commands, and many registers.
The model may also have hierarchy or be multicore and have other attributes and capabilities.
To see this information, please have a look at the model variant specific documents.
Click here to see the detailed document OVP_Model_Specific_Information_arm_MultiCluster.pdf.

Other Sites/Pages with similar information

Information on the MultiCluster OVP Fast Processor Model can also be found on other web sites:
www.imperas.com has more information on the model library.



ArmHoldingsProcessors
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