OVP Peripheral Model: National16550

Model Specific Information

This page provides introductory usage information for an Imperas OVP peripheral behavioral model. The page is split into sections providing specific information for this peripheral, including any ports for connecting into a platform, registers, other component parts, and configuration options and general information for peripheral modeling with Imperas OVP.


Open Source Apache 2.0


16550 UART model

The serial input/output from the simulator is implemented using the Serial Device Support described in OVP BHM and PPM API Functions Reference, which describes the parameters that control how the model interacts with the host computer.

Interrupts and FIFOs are supported.

Registers are aligned on 1 byte boundaries.


Resolution of the baud rate is limited to the simulation time slice (aka quantum) size.

Values written to the MCR are ignored. Loopback mode is not supported.

The LSR is read-only. The model never sets the LSR 'Parity Error', 'Framing Error', 'Break Interrupt' or 'Error in RCVR FIFO' bits.

The MSR 'Data Set Ready' and 'Clear To Send' bits are set at reset and all other MSR bits are cleared. MSR bits will only be changed by writes to the MSR and values written to the Modem Status Register do not effect the operation of the model.


PC16550D Universal Asynchronous Receiver/Transmitter with FIFOs datasheet (


The 16550 peripheral model is located in an Imperas/OVP installation at the VLNV: / peripheral / 16550 / 1.0.

Peripheral Instance Parameters

This model accepts the following parameters:

Table : Peripheral Parameters

uart16450boolRun in 16450 mode (no FIFOs)
fifoSizeuns32Size of fifos
refClkFrequns32Frequency (in hertz) of reference clock rate used in baud rate calculation
simulatebaudboolDescription Set to true to simulate baud delay determined by the Divisor Latch register value and reference clock frequency. Set to false to run without delay - next read data is made available immediately upon read of Receiver Buffer Register. Defaults to false
charmodeboolDescription Set to true when the port is used to connect to a Telnet program and character mode is desired rather than the default Telnet line mode. When set to true a Telnet command sequence is sent at startup that configures the Telnet program into character mode. In addition null bytes are stripped from the data received.
consoleboolIf specified, port number is ignored, and a console pops up automatically
clientboolIf true, model is a client and will connect to portnum. If false, model is a server and will listen on portnum.
portnumuns32If set, listen on, or connect to, this port. If set to zero in listen mode, allocate a port from the pool and listen on that.
hostnamestringName (or IP address) of host to connect to. Valid if listen=true
infilestringName of file to use for device source
outfilestringName of file to write device output
portFilestringIf portnum was specified as zero, write the port number to this file when it's known
logboolIf specified, serial output will go to simulator log
finishOnDisconnectboolIf set, disconnecting the port will cause the simulation to finish
connectnonblockingboolIf set, simulation can begin before the connection is made
xcharsuns32Width of console in characters
ycharsuns32Height of console in characters
recordstringRecord external events into this file
replaystringReplay external events from this file

Net Ports

This model has the following net ports:

Table 1: Net Ports

NameTypeMust Be ConnectedDescription
reset_uartinputF (False)
intOutoutputF (False)

Bus Slave Ports

This model has the following bus slave ports:

Bus Slave Port: bport1

Table 2: Bus Slave Port: bport1

NameSize (bytes)Must Be ConnectedDescription
bport10x8T (True)

Table 3: Bus Slave Port: bport1 Registers:

NameOffsetWidth (bits)DescriptionR/Wis Volatile
ab_rbr_dll0x08UART Receiver Buffer Register/Divisor Latch Low Read (LCR.DLAB=1)
ab_thr_dll0x08UART Transmitter Holding Register/Divisor Latch Low Write (LCR.DLAB=1)
ab_ier_dlh0x18UART Interrupt Enable Register/Divisor Latch High (LCR.DLAB=1)
ab_iir0x28UART Interrupt Identity Register
ab_fcr0x28UART FIFO Control Register
ab_lcr0x38UART Line Control Register
ab_mcr0x48UART MODEM Control Register
ab_lsr0x58UART Line Status Register
ab_msr0x68UART MODEM Status Register
ab_scr0x78UART Scratch Register

Platforms that use this peripheral component

Peripheral components can be used in many different platforms, including those developed by Imperas or by other users of OVP. You can use this peripheral in your own platforms.

Table 4: Publicly available platforms using peripheral '16550'

Platform NameVendor

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