| Name | Type | Description |
|---|---|---|
| finishOnDisconnect | bool | If set, disconnecting the port will cause the simulation to finish |
| outfile | string | Name of file to write device output |
| portFile | string | If portnum was specified as zero, write the port number to this file when it's known |
| log | bool | If specified, serial output will go to simulator log |
| console | bool | If specified, port number is ignored, and a console pops up automatically |
| portnum | uns32 | If set, listen on this port. If set to zero, allocate a port from the pool and listen on that. |
| infile | string | Name of file to use for device source |
| charmode | bool | Description Set to true when the port is used to connect to a Telnet program and character mode is desired rather than the default Telnet line mode. When set to true a Telnet command sequence is sent at startup that configures the Telnet program into character mode. In addition null bytes are stripped from the data received. |
| simulatebaud | bool | Description Set to true to simulate baud delay determined by the Divisor Latch register value and reference clock frequency. Set to false to run without delay - next read data is made available immediately upon read of Receiver Buffer Register. Defaults to false |
| refClkFreq | uns32 | Frequency (in hertz) of reference clock rate used in baud rate calculation |
| fifoSize | uns32 | Size of fifos |
| uart16450 | bool | Run in 16450 mode (no FIFOs) |
| connectnonblocking | bool | If set, simulation can begin before the connection is made |
| xchars | uns32 | Width of console in characters |
| ychars | uns32 | Height of console in characters |
| record | string | Record external events into this file |
| replay | string | Replay external events from this file |
LIBRARY | COMPANIES | PLATFORMS | PROCESSORS | PERIPHERALS
National16550
The LSR is read-only. The model never sets the LSR 'Parity Error', 'Framing Error', 'Break Interrupt' or 'Error in RCVR FIFO' bits.
Values written to the MCR are ignored. Loopback mode is not supported.
Registers are aligned on 1 byte boundaries.
NationalPeripherals
OVP Peripheral Model: National16550
Model Specific Information
This page provides introductory usage information for an Imperas OVP peripheral behavioral model. The page is split into sections providing specific information for this peripheral, including any ports for connecting into a platform, registers, other component parts, and configuration options and general information for peripheral modeling with Imperas OVP.Limitations
The MSR 'Data Set Ready' and 'Clear To Send' bits are set at reset and all other MSR bits are cleared. MSR bits will only be changed by writes to the MSR and values written to the Modem Status Register do not effect the operation of the model.The LSR is read-only. The model never sets the LSR 'Parity Error', 'Framing Error', 'Break Interrupt' or 'Error in RCVR FIFO' bits.
Values written to the MCR are ignored. Loopback mode is not supported.
Description
Interrupts and FIFOs are supported.Registers are aligned on 1 byte boundaries.
Limitations
Resolution of the baud rate is limited to the simulation time slice (aka quantum) size.Description
The serial input/output from the simulator is implemented using the Serial Device Support described in OVP BHM and PPM API Functions Reference, which describes the parameters that control how the model interacts with the host computer.Licensing
Open Source Apache 2.0Description
16550 UART modelReference
PC16550D Universal Asynchronous Receiver/Transmitter with FIFOs datasheet (http://www.ti.com/lit/ds/symlink/pc16550d.pdf)Location
The 16550 peripheral model is located in an Imperas/OVP installation at the VLNV: national.ovpworld.org / peripheral / 16550 / 1.0.Peripheral Instance Parameters
This model accepts the following parameters:Table : Peripheral Parameters
Net Ports
This model has the following net ports:Table 1: Net Ports
| Name | Type | Must Be Connected | Description |
|---|---|---|---|
| reset_uart | input | F (False) | |
| intOut | output | F (False) |
Bus Slave Ports
This model has the following bus slave ports:Bus Slave Port: bport1
Table 2: Bus Slave Port: bport1
| Name | Size (bytes) | Must Be Connected | Description |
|---|---|---|---|
| bport1 | 0x8 | T (True) |
Table 3: Bus Slave Port: bport1 Registers:
| Name | Offset | Width (bits) | Description | R/W | is Volatile |
|---|---|---|---|---|---|
| ab_lsr | 0x5 | 8 | UART Line Status Register | ||
| ab_lcr | 0x3 | 8 | UART Line Control Register | ||
| ab_mcr | 0x4 | 8 | UART MODEM Control Register | ||
| ab_fcr | 0x2 | 8 | UART FIFO Control Register | ||
| ab_iir | 0x2 | 8 | UART Interrupt Identity Register | ||
| ab_ier_dlh | 0x1 | 8 | UART Interrupt Enable Register/Divisor Latch High (LCR.DLAB=1) | ||
| ab_thr_dll | 0x0 | 8 | UART Transmitter Holding Register/Divisor Latch Low Write (LCR.DLAB=1) | ||
| ab_rbr_dll | 0x0 | 8 | UART Receiver Buffer Register/Divisor Latch Low Read (LCR.DLAB=1) | ||
| ab_msr | 0x6 | 8 | UART MODEM Status Register | ||
| ab_scr | 0x7 | 8 | UART Scratch Register |
Platforms that use this peripheral component
Peripheral components can be used in many different platforms, including those developed by Imperas or by other users of OVP. You can use this peripheral in your own platforms.Table 4: Publicly available platforms using peripheral '16550'
NationalPeripherals
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