OVP Peripheral Model: NxpIMX6GPIO
Model Specific Information
This page provides introductory usage information for an Imperas OVP peripheral behavioral model.
The page is split into sections providing specific information for this peripheral,
including any ports for connecting into a platform, registers, other component parts, and configuration options and general information for peripheral modeling with Imperas OVP.
Description
NXP i.MX6 GPIO
Licensing
Open Source Apache 2.0
Limitations
No behaviour is implemented.
Reference
i.MX 6Solo/6DualLite Applications Processor Reference Manual (IMX6SDLRM_Ref_Manual.pdf
Location
The iMX6_GPIO peripheral model is located in an Imperas/OVP installation at the VLNV: nxp.ovpworld.org / peripheral / iMX6_GPIO / 1.0.
Bus Slave Ports
This model has the following bus slave ports:
Bus Slave Port: bport1
Table : Bus Slave Port: bport1
Name | Size (bytes) | Must Be Connected | Description |
---|
bport1 | 0x4000 | T (True) | |
Table 1: Bus Slave Port: bport1 Registers:
Name | Offset | Width (bits) | Description | R/W | is Volatile |
---|
ab_DR | 0x0 | 32 | GPIO Data Register | | |
ab_GDIR | 0x4 | 32 | GPIO Direction Register | | |
ab_PSR | 0x8 | 32 | GPIO PAD Status Register | | |
ab_ICR1 | 0xc | 32 | GPIO interrupt configuration register1 | | |
ab_ICR2 | 0x10 | 32 | GPIO interrupt configuration register2 | | |
ab_IMR1 | 0x14 | 32 | GPIO interrupt mask register | | |
ab_ISR | 0x18 | 32 | GPIO interrupt status register | | |
ab_EDGE_SEL | 0x1c | 32 | GPIO edge select register | | |
Platforms that use this peripheral component
Peripheral components can be used in many different platforms, including those developed by Imperas or by other users of OVP. You can use this peripheral in your own platforms.
Table 2: Publicly available platforms using peripheral 'iMX6_GPIO'