| Name | Size (bytes) | Must Be Connected | Description |
|---|---|---|---|
| bport1 | 0x4000 | T (True) |
LIBRARY | COMPANIES | PLATFORMS | PROCESSORS | PERIPHERALS
NxpIMX6MMDC
NxpPeripherals
OVP Peripheral Model: NxpIMX6MMDC
Model Specific Information
This page provides introductory usage information for an Imperas OVP peripheral behavioral model. The page is split into sections providing specific information for this peripheral, including any ports for connecting into a platform, registers, other component parts, and configuration options and general information for peripheral modeling with Imperas OVP.Description
NXP i.MX6 MMDCLicensing
Open Source Apache 2.0Limitations
This is a register only model with acknowledgement of auto power savingReference
i.MX 6Solo/6DualLite Applications Processor Reference Manual (IMX6SDLRM_Ref_Manual.pdfLocation
The iMX6_MMDC peripheral model is located in an Imperas/OVP installation at the VLNV: nxp.ovpworld.org / peripheral / iMX6_MMDC / 1.0.Bus Slave Ports
This model has the following bus slave ports:Bus Slave Port: bport1
Table : Bus Slave Port: bport1
Table 1: Bus Slave Port: bport1 Registers:
| Name | Offset | Width (bits) | Description | R/W | is Volatile |
|---|---|---|---|---|---|
| ab_MMDC_MDCTL | 0x0 | 32 | MMDC Core Control Register | ||
| ab_MMDC_MDPDC | 0x4 | 32 | MMDC Core Power Down Control Register | ||
| ab_MMDC_MDOTC | 0x8 | 32 | MMDC Core ODT Timing Control Register | ||
| ab_MMDC_MDCFG0 | 0xc | 32 | MMDC Core Timing Configuration Register 0 | ||
| ab_MMDC_MDCFG1 | 0x10 | 32 | MMDC Core Timing Configuration Register 1 | ||
| ab_MMDC_MDCFG2 | 0x14 | 32 | MMDC Core Timing Configuration Register 2 | ||
| ab_MMDC_MDMISC | 0x18 | 32 | MMDC Core Miscellaneous Register | ||
| ab_MMDC_MDSCR | 0x1c | 32 | MMDC Core Special Command Register | ||
| ab_MMDC_MDREF | 0x20 | 32 | MMDC Core Refresh Control Register | ||
| ab_MMDC_MDRWD | 0x2c | 32 | MMDC Core Read/Write Command Delay Register | ||
| ab_MMDC_MDOR | 0x30 | 32 | MMDC Core Out of Reset Delays Register | ||
| ab_MMDC_MDMRR | 0x34 | 32 | MMDC Core MRR Data Register | ||
| ab_MMDC_MDCFG3LP | 0x38 | 32 | MMDC Core Timing Configuration Register 3 | ||
| ab_MMDC_MDMR4 | 0x3c | 32 | MMDC Core MR4 Derating Register | ||
| ab_MMDC_MDASP | 0x40 | 32 | MMDC Core Address Space Partition Register | ||
| ab_MMDC_MAARCR | 0x400 | 32 | MMDC Core AXI Reordering Control Register | ||
| ab_MMDC_MAPSR | 0x404 | 32 | Description MMDC Core Power Saving Control and Status Register DVFS/Self-Refresh acknowledge General low-power acknowledge DVFS/Self-Refresh request General LPMD request Automatic Power saving timer. Write Idle Status. Read Idle Status Power Saving Status Automatic Power Saving Disable | ||
| ab_MMDC_MAEXIDR0 | 0x408 | 32 | MMDC Core Exclusive ID Monitor Register0 | ||
| ab_MMDC_MAEXIDR1 | 0x40c | 32 | MMDC Core Exclusive ID Monitor Register1 | ||
| ab_MMDC_MADPCR0 | 0x410 | 32 | MMDC Core Debug and Profiling Control Register 0 | ||
| ab_MMDC_MADPCR1 | 0x414 | 32 | MMDC Core Debug and Profiling Control Register 1 | ||
| ab_MMDC_MADPSR0 | 0x418 | 32 | MMDC Core Debug and Profiling Status Register 0 | ||
| ab_MMDC_MADPSR1 | 0x41c | 32 | MMDC Core Debug and Profiling Status Register 1 | ||
| ab_MMDC_MADPSR2 | 0x420 | 32 | MMDC Core Debug and Profiling Status Register 2 | ||
| ab_MMDC_MADPSR3 | 0x424 | 32 | MMDC Core Debug and Profiling Status Register 3 | ||
| ab_MMDC_MADPSR4 | 0x428 | 32 | MMDC Core Debug and Profiling Status Register 4 | ||
| ab_MMDC_MADPSR5 | 0x42c | 32 | MMDC Core Debug and Profiling Status Register 5 | ||
| ab_MMDC_MASBS0 | 0x430 | 32 | MMDC Core Step By Step Address Register | ||
| ab_MMDC_MASBS1 | 0x434 | 32 | MMDC Core Step By Step Address Attributes Register | ||
| ab_MMDC_MAGENP | 0x440 | 32 | MMDC Core General Purpose Register | ||
| ab_MMDC_MPZQHWCTRL | 0x800 | 32 | MMDC PHY ZQ HW control register | ||
| ab_MMDC_MPZQSWCTRL | 0x804 | 32 | MMDC PHY ZQ SW control register | ||
| ab_MMDC_MPWLGCR | 0x808 | 32 | MMDC PHY Write Leveling Configuration and Error Status Register | ||
| ab_MMDC_MPWLDECTRL0 | 0x80c | 32 | MMDC PHY Write Leveling Delay Control Register 0 | ||
| ab_MMDC_MPWLDECTRL1 | 0x810 | 32 | MMDC PHY Write Leveling Delay Control Register 1 | ||
| ab_MMDC_MPWLDLST | 0x814 | 32 | MMDC PHY Write Leveling delay-line Status Register | ||
| ab_MMDC_MPODTCTRL | 0x818 | 32 | MMDC PHY ODT control register | ||
| ab_MMDC_MPRDDQBY0DL | 0x81c | 32 | MMDC PHY Read DQ Byte0 Delay Register | ||
| ab_MMDC_MPRDDQBY1DL | 0x820 | 32 | MMDC PHY Read DQ Byte1 Delay Register | ||
| ab_MMDC_MPRDDQBY2DL | 0x824 | 32 | MMDC PHY Read DQ Byte2 Delay Register | ||
| ab_MMDC_MPRDDQBY3DL | 0x828 | 32 | MMDC PHY Read DQ Byte3 Delay Register | ||
| ab_MMDC_MPWRDQBY0DL | 0x82c | 32 | MMDC PHY Write DQ Byte0 Delay Register | ||
| ab_MMDC_MPWRDQBY1DL | 0x830 | 32 | MMDC PHY Write DQ Byte1 Delay Register | ||
| ab_MMDC_MPWRDQBY2DL | 0x834 | 32 | MMDC PHY Write DQ Byte2 Delay Register | ||
| ab_MMDC_MPWRDQBY3DL | 0x838 | 32 | MMDC PHY Write DQ Byte3 Delay Register | ||
| ab_MMDC_MPDGCTRL0 | 0x83c | 32 | MMDC PHY Read DQS Gating Control Register 0 | ||
| ab_MMDC_MPDGCTRL1 | 0x840 | 32 | MMDC PHY Read DQS Gating Control Register 1 | ||
| ab_MMDC_MPDGDLST0 | 0x844 | 32 | MMDC PHY Read DQS Gating delay-line Status Register | ||
| ab_MMDC_MPRDDLCTL | 0x848 | 32 | MMDC PHY Read delay-lines Configuration Register | ||
| ab_MMDC_MPRDDLST | 0x84c | 32 | MMDC PHY Read delay-lines Status Register | ||
| ab_MMDC_MPWRDLCTL | 0x850 | 32 | MMDC PHY Write delay-lines Configuration Register | ||
| ab_MMDC_MPWRDLST | 0x854 | 32 | MMDC PHY Write delay-lines Status Register | ||
| ab_MMDC_MPSDCTRL | 0x858 | 32 | MMDC PHY CK Control Register | ||
| ab_MMDC_MPZQLP2CTL | 0x85c | 32 | MMDC ZQ LPDDR2 HW Control Register | ||
| ab_MMDC_MPRDDLHWCTL | 0x860 | 32 | MMDC PHY Read Delay HW Calibration Control Register | ||
| ab_MMDC_MPWRDLHWCTL | 0x864 | 32 | MMDC PHY Write Delay HW Calibration Control Register | ||
| ab_MMDC_MPRDDLHWST0 | 0x868 | 32 | MMDC PHY Read Delay HW Calibration Status Register 0 | ||
| ab_MMDC_MPRDDLHWST1 | 0x86c | 32 | MMDC PHY Read Delay HW Calibration Status Register 1 | ||
| ab_MMDC_MPWRDLHWST0 | 0x870 | 32 | MMDC PHY Write Delay HW Calibration Status Register 0 | ||
| ab_MMDC_MPWRDLHWST1 | 0x874 | 32 | MMDC PHY Write Delay HW Calibration Status Register 1 | ||
| ab_MMDC_MPWLHWERR | 0x878 | 32 | MMDC PHY Write Leveling HW Error Register | ||
| ab_MMDC_MPDGHWST0 | 0x87c | 32 | MMDC PHY Read DQS Gating HW Status Register 0 | ||
| ab_MMDC_MPDGHWST1 | 0x880 | 32 | MMDC PHY Read DQS Gating HW Status Register 1 | ||
| ab_MMDC_MPDGHWST2 | 0x884 | 32 | MMDC PHY Read DQS Gating HW Status Register 2 | ||
| ab_MMDC_MPDGHWST3 | 0x888 | 32 | MMDC PHY Read DQS Gating HW Status Register 3 | ||
| ab_MMDC_MPPDCMPR1 | 0x88c | 32 | MMDC PHY Pre-defined Compare Register 1 | ||
| ab_MMDC_MPPDCMPR2 | 0x890 | 32 | MMDC PHY Pre-defined Compare and CA delay-line Configuration Register | ||
| ab_MMDC_MPSWDAR0 | 0x894 | 32 | MMDC PHY SW Dummy Access Register | ||
| ab_MMDC_MPSWDRDR0 | 0x898 | 32 | MMDC PHY SW Dummy Read Data Register 0 | ||
| ab_MMDC_MPSWDRDR1 | 0x89c | 32 | MMDC PHY SW Dummy Read Data Register 1 | ||
| ab_MMDC_MPSWDRDR2 | 0x8a0 | 32 | MMDC PHY SW Dummy Read Data Register 2 | ||
| ab_MMDC_MPSWDRDR3 | 0x8a4 | 32 | MMDC PHY SW Dummy Read Data Register 3 | ||
| ab_MMDC_MPSWDRDR4 | 0x8a8 | 32 | MMDC PHY SW Dummy Read Data Register 4 | ||
| ab_MMDC_MPSWDRDR5 | 0x8ac | 32 | MMDC PHY SW Dummy Read Data Register 5 | ||
| ab_MMDC_MPSWDRDR6 | 0x8b0 | 32 | MMDC PHY SW Dummy Read Data Register 6 | ||
| ab_MMDC_MPSWDRDR7 | 0x8b4 | 32 | MMDC PHY SW Dummy Read Data Register 7 | ||
| ab_MMDC_MPMUR0 | 0x8b8 | 32 | MMDC PHY Measure Unit Register | ||
| ab_MMDC_MPWRCADL | 0x8bc | 32 | MMDC Write CA delay-line controller | ||
| ab_MMDC_MPDCCR | 0x8c0 | 32 | MMDC Duty Cycle Control Register |
Platforms that use this peripheral component
Peripheral components can be used in many different platforms, including those developed by Imperas or by other users of OVP. You can use this peripheral in your own platforms.Table 2: Publicly available platforms using peripheral 'iMX6_MMDC'
| Platform Name | Vendor |
|---|---|
| iMX6S | nxp.ovpworld.org |
NxpPeripherals
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