OVP Peripheral Model: NxpIMX6WDOG

Model Specific Information

This page provides introductory usage information for an Imperas OVP peripheral behavioral model. The page is split into sections providing specific information for this peripheral, including any ports for connecting into a platform, registers, other component parts, and configuration options and general information for peripheral modeling with Imperas OVP.




Open Source Apache 2.0


This is an incomplete model of the WDOG.

It has basic functionality to support the iMX6 platform.


i.MX 6Solo/6DualLite Applications Processor Reference Manual (IMX6SDLRM_Ref_Manual.pdf


The iMX6_WDOG peripheral model is located in an Imperas/OVP installation at the VLNV: / peripheral / iMX6_WDOG / 1.0.

Net Ports

This model has the following net ports:

Table : Net Ports

NameTypeMust Be ConnectedDescription
WDOGoutputF (False)WDOG failure
interruptoutputF (False)Interrupt line.
wdog_rstoutputF (False)WDOG Reset

Bus Slave Ports

This model has the following bus slave ports:

Bus Slave Port: bport1

Table 1: Bus Slave Port: bport1

NameSize (bytes)Must Be ConnectedDescription
bport10x4000T (True)

Table 2: Bus Slave Port: bport1 Registers:

NameOffsetWidth (bits)DescriptionR/Wis Volatile
ab_WDOG_WCR0x016Description Watchdog Control Register Watchdog Time-out Field (0.5 to 128 seconds) Watchdog Disable for Wait Software reset extension, an option way to generate software reset WDOG_B assertion. Controls the software assertion of the WDOG_B signal Software Reset Signal. Controls the software assertion of the WDOG-generated reset signal WDOG_RESET_B_DEB WDOG_B Time-out assertion. Determines if the WDOG_B gets asserted upon a Watchdog Time-out Event Watchdog Enable. Enables or disables the WDOG block Watchdog DEBUG Enable. Determines the operation of the WDOG during DEBUG mode Watchdog Low Power. Determines the operation of the WDOG during low-power modes
ab_WDOG_WSR0x216Watchdog Service Register
ab_WDOG_WRSR0x416Description Watchdog Reset Status Register Power On Reset. Indicates whether the reset is the result of a power on reset Timeout. Indicates whether the reset is the result of a WDOG timeout Software Reset. Indicates whether the reset is the result of a WDOG software reset by asserting SRS bit
ab_WDOG_WICR0x616Description Watchdog Interrupt Control Register Watchdog Timer Interrupt enable bit Watchdog TImer Interrupt Status bit will reflect the timer interrupt status Watchdog Interrupt Count Time-out (WICT) field determines, how long before the counter time-out must the interrupt occur
ab_WDOG_WMCR0x816Description Watchdog Miscellaneous Control Register Power Down Enable bit

Platforms that use this peripheral component

Peripheral components can be used in many different platforms, including those developed by Imperas or by other users of OVP. You can use this peripheral in your own platforms.

Table 3: Publicly available platforms using peripheral 'iMX6_WDOG'

Platform NameVendor

Page was generated in 0.0140 seconds