LIBRARY  |  COMPANIES |   PLATFORMS |   PROCESSORS |   PERIPHERALS
NxpIMX6_MMDC



OVP Peripheral Model: NxpIMX6_MMDC



Model Specific Information

This page provides introductory usage information for an Imperas OVP peripheral behavioral model. The page is split into sections providing specific information for this peripheral, including any ports for connecting into a platform, registers, other component parts, and configuration options and general information for peripheral modeling with Imperas OVP.

Reference

i.MX 6Solo/6DualLite Applications Processor Reference Manual (IMX6SDLRM_Ref_Manual.pdf

Limitations

This is a register only model with acknowledgement of auto power saving

Description

NXP i.MX6 MMDC

Licensing

Open Source Apache 2.0

Location

The iMX6_MMDC peripheral model is located in an Imperas/OVP installation at the VLNV: nxp.ovpworld.org / peripheral / iMX6_MMDC / 1.0.



Bus Slave Ports

This model has the following bus slave ports:

Bus Slave Port: bport1

Table : Bus Slave Port: bport1

NameSize (bytes)Must Be ConnectedDescription
bport10x4000T (True)

Table 1: Bus Slave Port: bport1 Registers:

NameOffsetWidth (bits)DescriptionR/Wis Volatile
ab_MMDC_MPDGHWST20x88432MMDC PHY Read DQS Gating HW Status Register 2
ab_MMDC_MPDGHWST10x88032MMDC PHY Read DQS Gating HW Status Register 1
ab_MMDC_MPDGHWST00x87c32MMDC PHY Read DQS Gating HW Status Register 0
ab_MMDC_MPWLHWERR0x87832MMDC PHY Write Leveling HW Error Register
ab_MMDC_MPWRDLHWST10x87432MMDC PHY Write Delay HW Calibration Status Register 1
ab_MMDC_MPWRDLHWST00x87032MMDC PHY Write Delay HW Calibration Status Register 0
ab_MMDC_MPRDDLHWST10x86c32MMDC PHY Read Delay HW Calibration Status Register 1
ab_MMDC_MPRDDLHWST00x86832MMDC PHY Read Delay HW Calibration Status Register 0
ab_MMDC_MPWRDLHWCTL0x86432MMDC PHY Write Delay HW Calibration Control Register
ab_MMDC_MPRDDLHWCTL0x86032MMDC PHY Read Delay HW Calibration Control Register
ab_MMDC_MPZQLP2CTL0x85c32MMDC ZQ LPDDR2 HW Control Register
ab_MMDC_MPWRDLCTL0x85032MMDC PHY Write delay-lines Configuration Register
ab_MMDC_MPWRDLST0x85432MMDC PHY Write delay-lines Status Register
ab_MMDC_MPSDCTRL0x85832MMDC PHY CK Control Register
ab_MMDC_MPRDDLST0x84c32MMDC PHY Read delay-lines Status Register
ab_MMDC_MPRDDLCTL0x84832MMDC PHY Read delay-lines Configuration Register
ab_MMDC_MPDGDLST00x84432MMDC PHY Read DQS Gating delay-line Status Register
ab_MMDC_MPDGCTRL10x84032MMDC PHY Read DQS Gating Control Register 1
ab_MMDC_MPDGCTRL00x83c32MMDC PHY Read DQS Gating Control Register 0
ab_MMDC_MPWRDQBY3DL0x83832MMDC PHY Write DQ Byte3 Delay Register
ab_MMDC_MPWRDQBY2DL0x83432MMDC PHY Write DQ Byte2 Delay Register
ab_MMDC_MPWRDQBY1DL0x83032MMDC PHY Write DQ Byte1 Delay Register
ab_MMDC_MPWRDQBY0DL0x82c32MMDC PHY Write DQ Byte0 Delay Register
ab_MMDC_MPRDDQBY3DL0x82832MMDC PHY Read DQ Byte3 Delay Register
ab_MMDC_MPRDDQBY2DL0x82432MMDC PHY Read DQ Byte2 Delay Register
ab_MMDC_MPRDDQBY1DL0x82032MMDC PHY Read DQ Byte1 Delay Register
ab_MMDC_MPRDDQBY0DL0x81c32MMDC PHY Read DQ Byte0 Delay Register
ab_MMDC_MPODTCTRL0x81832MMDC PHY ODT control register
ab_MMDC_MPWLDLST0x81432MMDC PHY Write Leveling delay-line Status Register
ab_MMDC_MPWLDECTRL10x81032MMDC PHY Write Leveling Delay Control Register 1
ab_MMDC_MPWLDECTRL00x80c32MMDC PHY Write Leveling Delay Control Register 0
ab_MMDC_MPWLGCR0x80832MMDC PHY Write Leveling Configuration and Error Status Register
ab_MMDC_MPZQSWCTRL0x80432MMDC PHY ZQ SW control register
ab_MMDC_MPZQHWCTRL0x80032MMDC PHY ZQ HW control register
ab_MMDC_MAGENP0x44032MMDC Core General Purpose Register
ab_MMDC_MASBS10x43432MMDC Core Step By Step Address Attributes Register
ab_MMDC_MASBS00x43032MMDC Core Step By Step Address Register
ab_MMDC_MADPSR50x42c32MMDC Core Debug and Profiling Status Register 5
ab_MMDC_MADPSR40x42832MMDC Core Debug and Profiling Status Register 4
ab_MMDC_MADPSR30x42432MMDC Core Debug and Profiling Status Register 3
ab_MMDC_MADPSR20x42032MMDC Core Debug and Profiling Status Register 2
ab_MMDC_MADPSR10x41c32MMDC Core Debug and Profiling Status Register 1
ab_MMDC_MADPSR00x41832MMDC Core Debug and Profiling Status Register 0
ab_MMDC_MADPCR10x41432MMDC Core Debug and Profiling Control Register 1
ab_MMDC_MADPCR00x41032MMDC Core Debug and Profiling Control Register 0
ab_MMDC_MAEXIDR10x40c32MMDC Core Exclusive ID Monitor Register1
ab_MMDC_MAEXIDR00x40832MMDC Core Exclusive ID Monitor Register0
ab_MMDC_MAPSR0x40432Description MMDC Core Power Saving Control and Status Register DVFS/Self-Refresh acknowledge General low-power acknowledge DVFS/Self-Refresh request General LPMD request Automatic Power saving timer. Write Idle Status. Read Idle Status Power Saving Status Automatic Power Saving Disable
ab_MMDC_MAARCR0x40032MMDC Core AXI Reordering Control Register
ab_MMDC_MDASP0x4032MMDC Core Address Space Partition Register
ab_MMDC_MDMR40x3c32MMDC Core MR4 Derating Register
ab_MMDC_MDMRR0x3432MMDC Core MRR Data Register
ab_MMDC_MDCFG3LP0x3832MMDC Core Timing Configuration Register 3
ab_MMDC_MDOR0x3032MMDC Core Out of Reset Delays Register
ab_MMDC_MDRWD0x2c32MMDC Core Read/Write Command Delay Register
ab_MMDC_MDREF0x2032MMDC Core Refresh Control Register
ab_MMDC_MDSCR0x1c32MMDC Core Special Command Register
ab_MMDC_MDMISC0x1832MMDC Core Miscellaneous Register
ab_MMDC_MDCFG20x1432MMDC Core Timing Configuration Register 2
ab_MMDC_MDCFG10x1032MMDC Core Timing Configuration Register 1
ab_MMDC_MDCFG00xc32MMDC Core Timing Configuration Register 0
ab_MMDC_MDOTC0x832MMDC Core ODT Timing Control Register
ab_MMDC_MDPDC0x432MMDC Core Power Down Control Register
ab_MMDC_MDCTL0x032MMDC Core Control Register
ab_MMDC_MPDGHWST30x88832MMDC PHY Read DQS Gating HW Status Register 3
ab_MMDC_MPPDCMPR10x88c32MMDC PHY Pre-defined Compare Register 1
ab_MMDC_MPPDCMPR20x89032MMDC PHY Pre-defined Compare and CA delay-line Configuration Register
ab_MMDC_MPSWDAR00x89432MMDC PHY SW Dummy Access Register
ab_MMDC_MPSWDRDR00x89832MMDC PHY SW Dummy Read Data Register 0
ab_MMDC_MPSWDRDR10x89c32MMDC PHY SW Dummy Read Data Register 1
ab_MMDC_MPSWDRDR20x8a032MMDC PHY SW Dummy Read Data Register 2
ab_MMDC_MPSWDRDR30x8a432MMDC PHY SW Dummy Read Data Register 3
ab_MMDC_MPSWDRDR40x8a832MMDC PHY SW Dummy Read Data Register 4
ab_MMDC_MPSWDRDR50x8ac32MMDC PHY SW Dummy Read Data Register 5
ab_MMDC_MPSWDRDR60x8b032MMDC PHY SW Dummy Read Data Register 6
ab_MMDC_MPSWDRDR70x8b432MMDC PHY SW Dummy Read Data Register 7
ab_MMDC_MPMUR00x8b832MMDC PHY Measure Unit Register
ab_MMDC_MPWRCADL0x8bc32MMDC Write CA delay-line controller
ab_MMDC_MPDCCR0x8c032MMDC Duty Cycle Control Register



Platforms that use this peripheral component

Peripheral components can be used in many different platforms, including those developed by Imperas or by other users of OVP. You can use this peripheral in your own platforms.

Table 2: Publicly available platforms using peripheral 'iMX6_MMDC'

Platform NameVendor
iMX6Snxp.ovpworld.org



NxpPeripherals
Page was generated in 0.0316 seconds