OVP Peripheral Model: OVPSerInt

Model Specific Information

This page provides introductory usage information for an Imperas OVP peripheral behavioral model. The page is split into sections providing specific information for this peripheral, including any ports for connecting into a platform, registers, other component parts, and configuration options and general information for peripheral modeling with Imperas OVP.


The serial interrupt control registers in the FDC 37M817 SuperIO device.


This is a register description only. The model does not contain any functionality.


Open Source Apache 2.0


SMsC FDC 37M817 SuperIO device datasheet


The SerInt peripheral model is located in an Imperas/OVP installation at the VLNV: / peripheral / SerInt / 1.0.

Bus Slave Ports

This model has the following bus slave ports:

Bus Slave Port: bport1

Table : Bus Slave Port: bport1

NameSize (bytes)Must Be ConnectedDescription
bport10x4T (True)

Table 1: Bus Slave Port: bport1 Registers:

NameOffsetWidth (bits)DescriptionR/Wis Volatile

Platforms that use this peripheral component

Peripheral components can be used in many different platforms, including those developed by Imperas or by other users of OVP. You can use this peripheral in your own platforms.

Table 2: Publicly available platforms using peripheral 'SerInt'

Platform NameVendor

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