OVP Peripheral Model: OVPSimpleDma

Model Specific Information

This page provides introductory usage information for an Imperas OVP peripheral behavioral model. The page is split into sections providing specific information for this peripheral, including any ports for connecting into a platform, registers, other component parts, and configuration options and general information for peripheral modeling with Imperas OVP.


Basic DMA Controller.


This model is a basic DMA engine example implementation, it does not conform to an actual device.


Open Source Apache 2.0


This is not based upon a real device


The SimpleDma peripheral model is located in an Imperas/OVP installation at the VLNV: / peripheral / SimpleDma / 1.0.

Net Ports

This model has the following net ports:

Table : Net Ports

NameTypeMust Be ConnectedDescription
INTTCoutputF (False)Interrupt Request when DMA operation is complete
RESETinputF (False)Peripheral Reset

Bus Master Ports

This model has the following bus master ports:

Bus Master Port: MWRITE

Table 1: MWRITE

NameAddress Width (bits)Description
MWRITE32DMA Registers Master Port - Write

Bus Master Port: MREAD

Table 2: MREAD

NameAddress Width (bits)Description
MREAD32DMA Registers Master Port - Read

Bus Slave Ports

This model has the following bus slave ports:

Bus Slave Port: DMACSP

Table 3: Bus Slave Port: DMACSP

NameSize (bytes)Must Be ConnectedDescription
DMACSP0x140T (True)DMA Registers Slave Port

Table 4: Bus Slave Port: DMACSP Registers:

NameOffsetWidth (bits)DescriptionR/Wis Volatile
ab32ch1_control0x12c32channel 1 control
ab32ch1_dstAddr0x12432channel 1 dest address
ab32ch1_srcAddr0x12032channel 1 source address
ab32ch0_config0x11032channel 0 configuration
ab32ch0_control0x10c32channel 0 control
ab32ch0_dstAddr0x10432channel 0 dest address
ab32ch0_srcAddr0x10032channel 0 source address
ab8_rawTCstatus0x148raw TC status
ab8_intTCstatus0x48internal TC status
ab32ch1_config0x13032channel 1 configuration

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