OVP Peripheral Model: RenesasClkgen

Model Specific Information

This page provides introductory usage information for an Imperas OVP peripheral behavioral model. The page is split into sections providing specific information for this peripheral, including any ports for connecting into a platform, registers, other component parts, and configuration options and general information for peripheral modeling with Imperas OVP.


Open Source Apache 2.0


Renesas Clock Generator


Register View Model Only


R01UH0128ED0700, Rev. 7.00, Oct 06, 2010


The clkgen peripheral model is located in an Imperas/OVP installation at the VLNV: / peripheral / clkgen / 1.0.

Bus Slave Ports

This model has the following bus slave ports:

Bus Slave Port: CLKGENP0

Table : Bus Slave Port: CLKGENP0

NameSize (bytes)Must Be ConnectedDescription
CLKGENP00x1F (False)

Table 1: Bus Slave Port: CLKGENP0 Registers:

NameOffsetWidth (bits)DescriptionR/Wis Volatile

Bus Slave Port: CLKGENP1

Table 2: Bus Slave Port: CLKGENP1

NameSize (bytes)Must Be ConnectedDescription
CLKGENP10x1F (False)

Table 3: Bus Slave Port: CLKGENP1 Registers:

NameOffsetWidth (bits)DescriptionR/Wis Volatile

Platforms that use this peripheral component

Peripheral components can be used in many different platforms, including those developed by Imperas or by other users of OVP. You can use this peripheral in your own platforms.

Table 4: Publicly available platforms using peripheral 'clkgen'

Platform NameVendor

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