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RenesasClkgen



OVP Peripheral Model: RenesasClkgen



Model Specific Information

This page provides introductory usage information for an Imperas OVP peripheral behavioral model. The page is split into sections providing specific information for this peripheral, including any ports for connecting into a platform, registers, other component parts, and configuration options and general information for peripheral modeling with Imperas OVP.

Reference

R01UH0128ED0700, Rev. 7.00, Oct 06, 2010

Limitations

Register View Model Only

Description

Renesas Clock Generator

Licensing

Open Source Apache 2.0

Location

The clkgen peripheral model is located in an Imperas/OVP installation at the VLNV: renesas.ovpworld.org / peripheral / clkgen / 1.0.



Bus Slave Ports

This model has the following bus slave ports:

Bus Slave Port: CLKGENP1

Table : Bus Slave Port: CLKGENP1

NameSize (bytes)Must Be ConnectedDescription
CLKGENP10x1F (False)

Table 1: Bus Slave Port: CLKGENP1 Registers:

NameOffsetWidth (bits)DescriptionR/Wis Volatile
reg0_CLM0x08

Bus Slave Port: CLKGENP0

Table 2: Bus Slave Port: CLKGENP0

NameSize (bytes)Must Be ConnectedDescription
CLKGENP00x1F (False)

Table 3: Bus Slave Port: CLKGENP0 Registers:

NameOffsetWidth (bits)DescriptionR/Wis Volatile
reg0_CANCKSEL0x08



Platforms that use this peripheral component

Peripheral components can be used in many different platforms, including those developed by Imperas or by other users of OVP. You can use this peripheral in your own platforms.

Table 4: Publicly available platforms using peripheral 'clkgen'

Platform NameVendor
RenesasUPD70F3441renesas.ovpworld.org
RenesasUPD70F3441renesas.ovpworld.org



RenesasPeripherals
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