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RenesasUPD70F3441Logic



OVP Peripheral Model: RenesasUPD70F3441Logic



Model Specific Information

This page provides introductory usage information for an Imperas OVP peripheral behavioral model. The page is split into sections providing specific information for this peripheral, including any ports for connecting into a platform, registers, other component parts, and configuration options and general information for peripheral modeling with Imperas OVP.

Limitations

No known limitations

Description

Renesas V850PHO3 / UPD70F3441 Glue Logic

Licensing

Open Source Apache 2.0

Reference

R01UH0128ED0700, Rev. 7.00, Oct 06, 2010

Location

The UPD70F3441Logic peripheral model is located in an Imperas/OVP installation at the VLNV: renesas.ovpworld.org / peripheral / UPD70F3441Logic / 1.0.



Net Ports

This model has the following net ports:

Table : Net Ports

NameTypeMust Be ConnectedDescription
INT99outputF (False)
INT75outputF (False)
INT7outputF (False)
INT6outputF (False)
INT1outputF (False)
INT0outputF (False)
NMIOUToutputF (False)
INTFLinputF (False)
INTDMA3inputF (False)
INTUC2REinputF (False)
INTCB0REinputF (False)
INTP13inputF (False)
INTUC2RinputF (False)
INTCB0RinputF (False)
INTUC2TinputF (False)
INTCB0TinputF (False)
INTBRG1inputF (False)
INTBRG0inputF (False)
INTUC1RinputF (False)
INTP5inputF (False)
INTUC0RinputF (False)
INTP4inputF (False)
INTOSDinputF (False)
INTDEDFRinputF (False)
INTDEDRinputF (False)
INTDEDFinputF (False)
NMIINinputF (False)
INT100outputF (False)
INT101outputF (False)
INT116outputF (False)



Bus Slave Ports

This model has the following bus slave ports:

Bus Slave Port: LOGICP3

Table 1: Bus Slave Port: LOGICP3

NameSize (bytes)Must Be ConnectedDescription
LOGICP30x1F (False)

Table 2: Bus Slave Port: LOGICP3 Registers:

NameOffsetWidth (bits)DescriptionR/Wis Volatile
reg0_PRCMD0x08

Bus Slave Port: LOGICP2

Table 3: Bus Slave Port: LOGICP2

NameSize (bytes)Must Be ConnectedDescription
LOGICP20xcF (False)

Table 4: Bus Slave Port: LOGICP2 Registers:

NameOffsetWidth (bits)DescriptionR/Wis Volatile
reg0_PESC50x08
reg0_ESOST50x28
reg0_PESC60x48
reg0_ESOST60x68
reg0_PESMK50x88
reg0_PESMK60xa8

Bus Slave Port: LOGICP1

Table 5: Bus Slave Port: LOGICP1

NameSize (bytes)Must Be ConnectedDescription
LOGICP10x76F (False)

Table 6: Bus Slave Port: LOGICP1 Registers:

NameOffsetWidth (bits)DescriptionR/Wis Volatile
reg0_PFC100x748
reg0_PFC90x728
reg0_PFC80x708
reg0_PFC70x6e8
reg0_PFC40x688
reg0_PFC20x648
reg0_PFC10x628
reg0_PMC110x568
reg0_PM110x368
reg0_P110x168
reg0_PMC100x548
reg0_PM100x348
reg0_P100x148
reg0_PMC90x528
reg0_PM90x328
reg0_P90x128
reg0_PMC80x508
reg0_PM80x308
reg0_P80x108
reg0_PMC70x4e8
reg0_PM70x2e8
reg0_P70xe8
reg0_PMC60x4c8
reg0_PM60x2c8
reg0_P60xc8
reg0_PMC50x4a8
reg0_PM50x2a8
reg0_P50xa8
reg0_PMC40x488
reg0_PM40x288
reg0_P40x88
reg0_PMC30x468
reg0_PM30x268
reg0_P30x68
reg0_PMC20x448
reg0_PM20x248
reg0_P20x48
reg0_PMC10x428
reg0_PM10x228
reg0_P10x28
reg0_LOGICP00x08

Bus Slave Port: LOGICP0

Table 7: Bus Slave Port: LOGICP0

NameSize (bytes)Must Be ConnectedDescription
LOGICP00x4F (False)

Table 8: Bus Slave Port: LOGICP0 Registers:

NameOffsetWidth (bits)DescriptionR/Wis Volatile
reg0_INTERRF0x28
reg0_INTSEL0x08



Platforms that use this peripheral component

Peripheral components can be used in many different platforms, including those developed by Imperas or by other users of OVP. You can use this peripheral in your own platforms.

Table 9: Publicly available platforms using peripheral 'UPD70F3441Logic'

Platform NameVendor
RenesasUPD70F3441renesas.ovpworld.org
RenesasUPD70F3441renesas.ovpworld.org



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