LIBRARY  |  COMPANIES |   PLATFORMS |   PROCESSORS |   PERIPHERALS
RiscvPLIC



OVP Peripheral Model: RiscvPLIC



Model Specific Information

This page provides introductory usage information for an Imperas OVP peripheral behavioral model. The page is split into sections providing specific information for this peripheral, including any ports for connecting into a platform, registers, other component parts, and configuration options and general information for peripheral modeling with Imperas OVP.

Licensing

Open Source Apache 2.0

Description

PLIC Interrupt Controller

Use parameters to configure specific implementation.

Default model is based on SiFive PLIC implementation details - other variations are available (e.g. Andes NCEPLIC100).

Reference

The RISC-V Instruction Set Manual Volume II: Privileged Architecture Version 1.10 (https://riscv.org/specifications/privileged-isa)

SiFive Freedom U540-C000 Manual FU540-C000-v1.0.pdf (https://www.sifive.com/documentation/chips/freedom-u540-c000-manual)

Location

The PLIC peripheral model is located in an Imperas/OVP installation at the VLNV: riscv.ovpworld.org / peripheral / PLIC / 1.0.



Peripheral Instance Parameters

This model accepts the following parameters:

Table : Peripheral Parameters

NameTypeDescription
num_sourcesuns32Number of Input Interrupt Sources
num_targetsuns32Number of Output Interrupt Targets, Hart/Context
num_prioritiesuns32Number of Priority levels
priority_baseuns32Base Address offset for Priority Registers
pending_baseuns32Base Address offset for Pending Registers
enable_baseuns32Base Address offset for Enable Registers
enable_strideuns32Stride size for Enable Register Block
context_baseuns32Base Address offset for Context Registers, Threshold/Claim
context_strideuns32Stride size for Context Register Block



Net Ports

This model has the following net ports:

Table 1: Net Ports

NameTypeMust Be ConnectedDescription
irqS1inputF (False)
irqT0outputF (False)



Bus Slave Ports

This model has the following bus slave ports:

Bus Slave Port: port0

Table 2: Bus Slave Port: port0

NameSize (bytes)Must Be ConnectedDescription
port00x4000000F (False)

Table 3: Bus Slave Port: port0 Registers:

NameOffsetWidth (bits)DescriptionR/Wis Volatile
Priority10x432Priority of Input Interrupt Source 1
Pending00x100032Pending Interrupt Register for Interrupts 31 downto 0
Target0_Enable00x200032Target 0: Enable Register for Interrupts 31 downto 0
Target0_Threshold0x20000032Target 0 Priority Threshold
Target0_Claim0x20000432Target 0 Claim for Source



Platforms that use this peripheral component

Peripheral components can be used in many different platforms, including those developed by Imperas or by other users of OVP. You can use this peripheral in your own platforms.

Table 4: Publicly available platforms using peripheral 'PLIC'

Platform NameVendor
RiscvRV32FreeRTOSimperas.ovpworld.org
virtioriscv.ovpworld.org
FU540sifive.ovpworld.org
S51CCsifive.ovpworld.org



RiscVperipherals
Page was generated in 0.1246 seconds