OVP Virtual Platform: Zynq_PL_TTELNoC_node
This page provides detailed information about the OVP Virtual Platform Model of the
safepower.ovpworld.org Zynq_PL_TTELNoC_node platform.
Licensing
Open Source Apache 2.0
Description
This module implements a NoC ni used to implement an example TTEL NoC in the Xilinx Zynq Programmable Logic (PL).
This PL configuration instances one Xilinx MicroBlaze processor with a local memory and a TTEL NoC interface peripheral.
Limitations
This is baremetal only.
Reference
No Reference
Location
The Zynq_PL_TTELNoC_node virtual platform is located in an Imperas/OVP installation at the VLNV: safepower.ovpworld.org / module / Zynq_PL_TTELNoC_node / 1.0.
Platform Summary
Table : Components in platform
Platform Simulation Attributes
Table 1: Platform Simulation Attributes
| Attribute | Value | Description |
|---|
| stoponctrlc | stoponctrlc | Stop on control-C |
External Ports for Module Zynq_PL_TTELNoC_node
Table 2: External Ports
| Port Type | Port Name | Internal Connection |
|---|
| packetnetport | networkNodePort | networkNode |
Processor [xilinx.ovpworld.org/processor/microblaze/1.0] instance: cpu
Instance Parameters
Several parameters can be specified when a processor is instanced in a platform. For this processor instance 'cpu' it has been instanced with the following parameters:
Table 3: Processor Instance 'cpu' Parameters (Configurations)
| Parameter | Value | Description |
|---|
| mips | 100 | The nominal MIPS for the processor |
Memory Map for processor 'cpu' bus: 'pBus'
Processor instance 'cpu' is connected to bus 'pBus' using master port 'INSTRUCTION'.
Processor instance 'cpu' is connected to bus 'pBus' using master port 'DATA'.
Table 4: Memory Map ( 'cpu' / 'pBus' [width: 32] )
| Lo Address | Hi Address | Instance | Component |
|---|
| 0x0 | 0x3FFFFFF | ramS | ram |
| 0x80000000 | 0x80FFFFFF | ni | TTELNode |
Net Connections to processor: 'cpu'
There are no nets connected to this processor.
Peripheral Instances
Peripheral [safepower.ovpworld.org/peripheral/TTELNode/1.0] instance: ni
Description
The TTEL Network on Chip (NoC) node peripheral for SafePower Project
Licensing
Open Source Apache 2.0
Limitations
This model implements the TTEL NoC node processor interface. It does not model any timing in the transfer of messages between nodes.
Reference
Generated using document TTEL Software Extensions ver 1.0 and D1.2.1 architectural style of dreams r1-0.
Table 5: Configuration options (attributes) set for instance 'ni'
| Attributes | Value |
|---|
| cluster | cluster |
| tile | tile |
| node | node |
