OVP Virtual Platform: Zynq_PL_TTELNoC_sensor_actor_node_public_demonstrator
This page provides detailed information about the OVP Virtual Platform Model of the
safepower.ovpworld.org Zynq_PL_TTELNoC_sensor_actor_node_public_demonstrator platform.
Licensing
Open Source Apache 2.0
Description
This module implements a Sensor/Actor Node for the SafePower Public Demonstrator in the Xilinx Zynq Programmable Logic (PL).
This PL configuration instances one Xilinx MicroBlaze processor with a local memory and a TTEL NoC interface peripheral.
Limitations
Provides a baremetal implementation.
Reference
SafePower Public Demonstrator
Location
The Zynq_PL_TTELNoC_sensor_actor_node_public_demonstrator virtual platform is located in an Imperas/OVP installation at the VLNV: safepower.ovpworld.org / module / Zynq_PL_TTELNoC_sensor_actor_node_public_demonstrator / 1.0.
Platform Summary
Table : Components in platform
Platform Simulation Attributes
Table 1: Platform Simulation Attributes
Attribute | Value | Description |
---|
stoponctrlc | stoponctrlc | Stop on control-C |
External Ports for Module Zynq_PL_TTELNoC_sensor_actor_node_public_demonstrator
Table 2: External Ports
Port Type | Port Name | Internal Connection |
---|
packetnetport | networkNodePort | networkNode |
Processor [xilinx.ovpworld.org/processor/microblaze/1.0] instance: cpu
Instance Parameters
Several parameters can be specified when a processor is instanced in a platform. For this processor instance 'cpu' it has been instanced with the following parameters:
Table 3: Processor Instance 'cpu' Parameters (Configurations)
Parameter | Value | Description |
---|
mips | 100 | The nominal MIPS for the processor |
Table 4: Processor Instance 'cpu' Parameters (Attributes)
Parameter Name | Value | Type |
---|
C_ENDIANNESS | 1 | uns32 |
C_USE_INTERRUPT | 1 | uns32 |
C_INTERCONNECT | 2 | uns32 |
C_USE_FPU | 1 | uns32 |
C_USE_HW_MUL | 2 | uns32 |
C_USE_DIV | 1 | boolean |
Memory Map for processor 'cpu' bus: 'pBus'
Processor instance 'cpu' is connected to bus 'pBus' using master port 'INSTRUCTION'.
Processor instance 'cpu' is connected to bus 'pBus' using master port 'DATA'.
Table 5: Memory Map ( 'cpu' / 'pBus' [width: 32] )
Lo Address | Hi Address | Instance | Component |
---|
0x0 | 0x3FFFFFF | ramS | ram |
0x40000000 | 0x4003FFFF | debug_gpio_led_gimbal | ram |
0x40600000 | 0x4060000F | uart | xps-uartlite |
0x40800000 | 0x4080FFFF | iic_imu | ram |
0x40810000 | 0x4081FFFF | iic_bu | ram |
0x40820000 | 0x4082FFFF | iic_motor | ram |
0x41200000 | 0x412001FF | intc | axi-intc |
0x41C00000 | 0x41C0001F | timer | axi-timer |
0x44A00000 | 0x44A0FFFF | ppm | ram |
0x44A10000 | 0x44A1FFFF | spi_bg | ram |
0x44A20000 | 0x44A2FFFF | xadc | ram |
0x44A30000 | 0x44A3FFFF | clock_control | ram |
0x44A40000 | 0x44A4FFFF | ttel_clock | ram |
0x80000000 | 0x80FFFFFF | ni | TTELNode |
Net Connections to processor: 'cpu'
Table 6: Processor Net Connections ( 'cpu' )
Net Port | Net | Instance | Component |
---|
Interrupt | intc_mb | intc | axi-intc |
Peripheral Instances
Peripheral [safepower.ovpworld.org/peripheral/TTELNode/1.0] instance: ni
Description
The TTEL Network on Chip (NoC) node peripheral for SafePower Project
Licensing
Open Source Apache 2.0
Limitations
This model implements the TTEL NoC node processor interface. It does not model any timing in the transfer of messages between nodes.
Reference
Generated using document TTEL Software Extensions ver 1.0 and D1.2.1 architectural style of dreams r1-0.
Table 7: Configuration options (attributes) set for instance 'ni'
Attributes | Value |
---|
cluster | cluster |
tile | tile |
node | node |
Peripheral [xilinx.ovpworld.org/peripheral/axi-intc/1.0] instance: intc
Description
Microblaze LogiCORE IP AXI Interrupt Controller
Licensing
Open Source Apache 2.0
Limitations
Implements the basic interrupt processing behavior
Does not implement interrupt cascade
Reference
PG099 October 4, 2017 v4.1
There are no configuration options set for this peripheral instance.
Peripheral [xilinx.ovpworld.org/peripheral/axi-timer/1.0] instance: timer
Description
Xilinx AXI Timer
Licensing
Open Source Apache 2.0
Limitations
Resolution of this timer is limited to the simulation time slice (aka quantum) size
Reference
pg079-axi-timer, Vivado Design Suite, October t, 2016
Table 8: Configuration options (attributes) set for instance 'timer'
Attributes | Value |
---|
endian | little |
frequency | 100.000000 |
Peripheral [xilinx.ovpworld.org/peripheral/xps-uartlite/1.0] instance: uart
Description
Xilinx Uart-Lite
Limitations
Register Accurate & Functional Model
Licensing
Open Source Apache 2.0
Reference
DS573 Jun 22, 2011 v1.02.a
Table 9: Configuration options (attributes) set for instance 'uart'
Attributes | Value |
---|
endian | little |
finishOnDisconnect | 1 |