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SiFiveS21

Model Information


This page provides detailed information about the OVP Fast Processor Model of the SiFive S21 core.
Processor IP owner is SiFive. More information is available from them here.

OVP Fast Processor Model is written in C.
Provides a C API for use in C based platforms.
Provides a native C++ interface for use in SystemC TLM2 platforms.

The model is written using the OVP VMI API that provides a Virtual Machine Interface that defines the behavior of the processor.
The VMI API makes a clear line between model and simulator allowing very good optimization and world class high speed performance.

The model is provided as a binary shared object and is also available as source (different models have different licensing conditions). This allows the download and use of the model binary or the use of the source to explore and modify the model.

The model has been run through an extensive QA and regression testing process.

Parallel Simulation using Imperas QuantumLeap


Traditionally, processor models and simulators make use of one thread on the host PC. Imperas have developed a technology, called QuantumLeap, that makes use of the many host cores found in modern PC/workstations to achieve industry leading simulation performance. To find out about the Imperas parallel simulation lookup Imperas QuantumLeap. There are videos of QuantumLeap on ARM here, and MIPS here. For press information related to QuantumLeap for ARM click here or for MIPS click here.
Many of the OVP Fast Processor Models have been qualified to work with QuantumLeap - this is indicated for this model below.

Embedded Software Development tools


This model executes instructions of the target architecture and provides an interface for debug access. An interface to GDB is provided and this allows the connection of many industry standard debuggers that use the GDB/RSP interface. For more information watch the OVP video here.
The model also works with the Imperas Multicore Debugger and advanced Verification, Analysis and Profiling tools.

Instruction Set Simulator (ISS) for SiFive S21


An ISS is a software development tool that takes in instructions for a target processor and executes them. The heart of an ISS is the model of the processor. Imperas has developed a range of ISS products for use in embedded software development that utilize this fast Fast Processor Model. The Imperas SiFive S21 ISS runs on Windows/Linux x86 systems and takes a cross compiled elf file of your program and allows very fast execution. The SiFive S21 ISS also provides access to standard GDB/RSP debuggers and connects to the Eclipse IDE and Imperas debuggers.

Overview of SiFive S21 Fast Processor Model


Model Variant name: S21
Description:
    RISC-V S21 64-bit processor model
Licensing:
    This Model is released under the Open Source Apache 2.0
Extensions Enabled by Default:
    The model has the following architectural extensions enabled, and the corresponding bits in the misa CSR Extensions field will be set upon reset:
    misa bit 0: extension A (atomic instructions)
    misa bit 1: extension B (bit manipulation extension)
    misa bit 2: extension C (compressed instructions)
    misa bit 8: RV32I/RV64I/RV128I base integer instruction set
    misa bit 12: extension M (integer multiply/divide instructions)
    misa bit 20: extension U (User mode)
    To specify features that can be dynamically enabled or disabled by writes to the misa register in addition to those listed above, use parameter "add_Extensions_mask". This is a string parameter containing the feature letters to add; for example, value "DV" indicates that double-precision floating point and the Vector Extension can be enabled or disabled by writes to the misa register, if supported on this variant. Parameter "sub_Extensions_mask" can be used to disable dynamic update of features in the same way.
    Legacy parameter "misa_Extensions_mask" can also be used. This Uns32-valued parameter specifies all writable bits in the misa Extensions field, replacing any permitted bits defined in the base variant.
    Note that any features that are indicated as present in the misa mask but absent in the misa will be ignored. See the next section.
Enabling Other Extensions:
    The following extensions are supported by the model, but not enabled by default in this variant:
    misa bit 3: extension D (double-precision floating point)
    misa bit 5: extension F (single-precision floating point)
    To add features from this list to the visible set in the misa register, use parameter "add_Extensions". This is a string containing identification letters of features to enable; for example, value "DV" indicates that double-precision floating point and the Vector Extension should be enabled, if they are currently absent and are available on this variant.
    Legacy parameter "misa_Extensions" can also be used. This Uns32-valued parameter specifies the reset value for the misa CSR Extensions field, replacing any permitted bits defined in the base variant.
    To add features from this list to the implicitly-enabled set (not visible in the misa register), use parameter "add_implicit_Extensions". This is a string parameter in the same format as the "add_Extensions" parameter described above.
Disabling Extensions:
    The following extensions are enabled by default in the model and can be disabled:
    misa bit 0: extension A (atomic instructions)
    misa bit 1: extension B (bit manipulation extension)
    misa bit 12: extension M (integer multiply/divide instructions)
    misa bit 20: extension U (User mode)
    To disable features that are enabled by default, use parameter "sub_Extensions". This is a string containing identification letters of features to disable; for example, value "DF" indicates that double-precision and single-precision floating point extensions should be disabled, if they are enabled by default on this variant.
    To remove features from this list from the implicitly-enabled set (not visible in the misa register), use parameter "sub_implicit_Extensions". This is a string parameter in the same format as the "sub_Extensions" parameter described above.
Multicore Features:
    This is a multicore variant with 1 harts by default. The number of harts may be overridden with the "numHarts" parameter.
mtvec CSR:
    On this variant, the Machine trap-vector base-address register (mtvec) is writable. It can instead be configured as read-only using parameter "mtvec_is_ro".
    Values written to "mtvec" are masked using the value 0x3fffffffff. A different mask of writable bits may be specified using parameter "mtvec_mask" if required. In addition, when Vectored interrupt mode is enabled, parameter "tvec_align" may be used to specify additional hardware-enforced base address alignment. In this variant, "tvec_align" defaults to 64.
    If parameter "mtvec_sext" is True, values written to "mtvec" are sign-extended from the most-significant writable bit. In this variant, "mtvec_sext" is False, indicating that "mtvec" is not sign-extended.
    The initial value of "mtvec" is 0x0. A different value may be specified using parameter "mtvec" if required.
Reset:
    On reset, the model will restart at address 0x0. A different reset address may be specified using parameter "reset_address" or applied using optional input port "reset_addr" if required.
NMI:
    On an NMI, the model will restart at address 0x0; a different NMI address may be specified using parameter "nmi_address" or applied using optional input port "nmi_addr" if required. The cause reported on an NMI is 0x2 by default; a different cause may be specified using parameter "ecode_nmi" or applied using optional input port "nmi_cause" if required.
    If parameter "rnmi_version" is not "none", resumable NMIs are supported, managed by additional CSRs "mnscratch", "mnepc", "mncause" and "mnstatus", following the indicated version of the Resumable NMI extension proposal. In this variant, "rnmi_version" is "0.2.1".
    The NMI input is level-sensitive. To instead specify that the NMI input is latched on the rising edge of the NMI signal, set parameter "nmi_is_latched" to True.
WFI:
    WFI will halt the processor until an interrupt occurs. It can instead be configured as a NOP using parameter "wfi_is_nop". WFI timeout wait is implemented with a time limit of 0 (i.e. WFI causes an Illegal Instruction trap in Supervisor mode when mstatus.TW=1).
cycle CSR:
    The "cycle" CSR is implemented in this variant. Set parameter "cycle_undefined" to True to instead specify that "cycle" is unimplemented and accesses should cause Illegal Instruction traps.
instret CSR:
    The "instret" CSR is implemented in this variant. Set parameter "instret_undefined" to True to instead specify that "instret" is unimplemented and accesses should cause Illegal Instruction traps.
hpmcounter CSR:
    The "hpmcounter" CSRs are implemented in this variant. Set parameter "hpmcounter_undefined" to True to instead specify that "hpmcounter" CSRs are unimplemented and accesses should cause Illegal Instruction traps.
time CSR:
    The "time" CSR is not implemented in this variant and reads of it will cause Illegal Instruction traps. Set parameter "time_undefined" to False to instead specify that "time" is implemented.
mcycle CSR:
    The "mcycle" CSR is implemented in this variant. Set parameter "mcycle_undefined" to True to instead specify that "mcycle" is unimplemented and accesses should cause Illegal Instruction traps.
minstret CSR:
    The "minstret" CSR is implemented in this variant. Set parameter "minstret_undefined" to True to instead specify that "minstret" is unimplemented and accesses should cause Illegal Instruction traps.
mhpmcounter CSR:
    The "mhpmcounter" CSRs are implemented in this variant. Set parameter "mhpmcounter_undefined" to True to instead specify that "mhpmcounter" CSRs are unimplemented and accesses should cause Illegal Instruction traps.
Unaligned Accesses:
    Unaligned memory accesses are not supported by this variant. Set parameter "unaligned" to "T" to enable such accesses.
    Unaligned memory accesses are not supported for AMO instructions by this variant. Set parameter "unalignedAMO" to "T" to enable such accesses.
    Address misaligned exceptions are higher priority than page fault or access fault exceptions on this variant. Set parameter "unaligned_low_pri" to "T" to specify that they are lower priority instead.
PMP:
    8 PMP entries are implemented by this variant. Use parameter "PMP_registers" to specify a different number of PMP entries; set the parameter to 0 to disable the PMP unit. The PMP grain size (G) is 0, meaning that PMP regions as small as 4 bytes are implemented. Use parameter "PMP_grain" to specify a different grain size if required. Unaligned PMP accesses are not decomposed into separate aligned accesses; use parameter "PMP_decompose" to modify this behavior if required. Parameters to change the write masks for the PMP CSRs are not enabled; use parameter "PMP_maskparams" to modify this behavior if required. Parameters to change the reset values for the PMP CSRs are not enabled; use parameter "PMP_initialparams" to modify this behavior if required
    Accesses to unimplemented PMP registers are write-ignored and read as zero on this variant. Set parameter "PMP_undefined" to True to indicate that such accesses should cause Illegal Instruction exceptions instead.
LR/SC Granule:
    LR/SC instructions are implemented with a 64-byte reservation granule. A different granule size may be specified using parameter "lr_sc_grain".
Compressed Extension:
    Standard compressed instructions are present in this variant. Legacy compressed extension features may also be configured using parameters described below. Use parameter "commpress_version" to enable more recent compressed extension features if required.
    Parameter Zcea_version is used to specify the version of Zcea instructions present. By default, Zcea_version is set to "none" in this variant. Updates to this parameter require a commercial product license.
    Parameter Zceb_version is used to specify the version of Zceb instructions present. By default, Zceb_version is set to "none" in this variant. Updates to this parameter require a commercial product license.
    Parameter Zcee_version is used to specify the version of Zcee instructions present. By default, Zcee_version is set to "none" in this variant. Updates to this parameter require a commercial product license.
Privileged Architecture:
    This variant implements the Privileged Architecture with version specified in the References section of this document. Note that parameter "priv_version" can be used to select the required architecture version; see the following sections for detailed information about differences between each supported version.
Legacy Version 1.10:
    1.10 version of May 7 2017.
Version 20190608:
    Stable 1.11 version of June 8 2019, with these changes compared to version 1.10:
    - mcountinhibit CSR defined;
    - pages are never executable in Supervisor mode if page table entry U bit is 1;
    - mstatus.TW is writable if any lower-level privilege mode is implemented (previously, it was just if Supervisor mode was implemented);
Version 20211203:
    1.12 draft version of December 3 2021, with these changes compared to version 20190608:
    - mstatush, mseccfg, mseccfgh, menvcfg, menvcfgh, senvcfg, henvcfg, henvcfgh and mconfigptr CSRs defined;
    - xret instructions clear mstatus.MPRV when leaving Machine mode if new mode is less privileged than M-mode;
    - maximum number of PMP registers increased to 64;
    - data endian is now configurable.
Version 1.12:
    Official 1.12 version, identical to 20211203.
Version master:
    Unstable master version, currently identical to 1.12.
    Unstable master version, with these changes compared to version 1.0.0:
    - any subset may be enabled;
    - xperm.n, xperm.b, xperm.h and xperm.w instructions renamed xperm4, xperm8, xperm16 and xperm32.
Unprivileged Architecture:
    This variant implements the Unprivileged Architecture with version specified in the References section of this document. Note that parameter "user_version" can be used to select the required architecture version; see the following sections for detailed information about differences between each supported version.
Legacy Version 2.2:
    2.2 version of May 7 2017.
Version 20191213:
    Stable 20191213-Base-Ratified version of December 13 2019, with these changes compared to version 2.2:
    - floating point fmin/fmax instruction behavior modified to comply with IEEE 754-201x.
    - numerous other optional behaviors can be separately enabled using Z-prefixed parameters.
Bit-Manipulation Extension:
    This variant implements the Bit-Manipulation extension with version specified in the References section of this document. Note that parameter "bitmanip_version" can be used to select the required version of this extension. See section "Bit-Manipulation Extension Versions" for detailed information about differences between each supported version.
Bit-Manipulation Extension Parameters:
    Parameter Zbb is used to specify that the base instructions are present. By default, Zbb is set to 1 in this variant. Updates to this parameter require a commercial product license.
    Parameter Zba is used to specify that address calculation instructions are present. By default, Zba is set to 1 in this variant. Updates to this parameter require a commercial product license.
    Parameter Zbc is used to specify that carryless operation instructions are present. By default, Zbc is set to 0 in this variant. Updates to this parameter require a commercial product license.
    Parameter Zbe is used to specify that bit deposit/extract instructions are present. By default, Zbe is set to 0 in this variant. Updates to this parameter require a commercial product license. This parameter is ignored for version 1.0.0, which does not implement that subset.
    Parameter Zbf is used to specify that bit field place instructions are present. By default, Zbf is set to 0 in this variant. Updates to this parameter require a commercial product license. This parameter is ignored for version 1.0.0, which does not implement that subset.
    Parameter Zbm is used to specify that bit matrix operation instructions are present. By default, Zbm is set to 0 in this variant. Updates to this parameter require a commercial product license. This parameter is ignored for version 1.0.0, which does not implement that subset.
    Parameter Zbp is used to specify that permutation instructions are present. By default, Zbp is set to 0 in this variant. Updates to this parameter require a commercial product license. This parameter is ignored for version 1.0.0, which does not implement that subset.
    Parameter Zbr is used to specify that CRC32 instructions are present. By default, Zbr is set to 0 in this variant. Updates to this parameter require a commercial product license. This parameter is ignored for version 1.0.0, which does not implement that subset.
    Parameter Zbs is used to specify that single bit instructions are present. By default, Zbs is set to 0 in this variant. Updates to this parameter require a commercial product license.
    Parameter Zbt is used to specify that ternary instructions are present. By default, Zbt is set to 0 in this variant. Updates to this parameter require a commercial product license. This parameter is ignored for version 1.0.0, which does not implement that subset.
Bit-Manipulation Extension Versions:
    The Bit-Manipulation Extension specification has been under active development. To enable simulation of hardware that may be based on an older version of the specification, the model implements behavior for a number of previous versions of the specification. The differing features of these are listed below, in chronological order.
Version 0.90:
    Stable 0.90 version of June 10 2019.
Version 0.91:
    Stable 0.91 version of August 29 2019, with these changes compared to version 0.90:
    - change encodings of bmatxor, grev, grevw, grevi and greviw;
    - add gorc, gorcw, gorci, gorciw, bfp and bfpw instructions.
Version 0.92:
    Stable 0.92 version of November 8 2019, with these changes compared to version 0.91:
    - add packh, packu and packuw instructions;
    - add sext.b and sext.h instructions;
    - change encoding and behavior of bfp and bfpw instructions;
    - change encoding of bdep and bdepw instructions.
Version 0.93-draft:
    Draft 0.93 version of January 29 2020, with these changes compared to version 0.92:
    - add sh1add, sh2add, sh3add, sh1addu, sh2addu and sh3addu instructions;
    - move slo, sloi, sro and sroi to Zbp subset;
    - add orc16 to Zbb subset.
Version 0.93:
    Stable 0.93 version of January 10 2021, with these changes compared to version 0.93-draft:
    - assignments of instructions to Z extension groups changed;
    - exchange encodings of max and minu instructions;
    - add xperm.[nbhw] instructions;
    - instructions named *u.w renamed to *.uw;
    - instruction add.uw zero-extends argument rs1, not rs2;
    - instructions named sb* renamed to b*;
    - instructions named pcnt* renamed to cpop*;
    - instructions subu.w, addiwu, addwu, subwu, clmulw, clmulrw and clmulhw removed;
    - instructions slo, sro, sloi, sroi, slow, srow, sloiw and sroiw removed from all Z extension groups and are therefore never implemented;
    - instructions bext/bdep renamed to bcompress/bdecompress (this change is documented under the draft 0.94 version but is required to resolve an instruction name conflict introduced by instruction renames above);
Version 0.94:
    Stable 0.94 version of January 20 2021, with these changes compared to version 0.93:
    - instructions bset[i]w, bclr[i]w, binv[i]w and bextw removed.
Version 1.0.0:
    Stable 1.0.0 version of June 6 2021, with these changes compared to version 0.94:
    - instructions with immediate shift operands now follow base architecture semantics to determine operand legality instead of masking to XLEN-1;
    - only subsets Zba, Zbb, Zbc and Zbs may be enabled;
    - if the B extension is present, it is implicitly always enabled and not subject to control by misa.B, which is zero.
Other Extensions:
    Other extensions that can be configured are described in this section.
Zmmul:
    Parameter "Zmmul" is 0 on this variant, meaning that all multiply and divide instructions are implemented. if "Zmmul" is set to 1 then multiply instructions are implemented but divide and remainder instructions are not implemented.
Zicsr:
    Parameter "Zicsr" is 1 on this variant, meaning that standard CSRs and CSR access instructions are implemented. if "Zicsr" is set to 0 then standard CSRs and CSR access instructions are not implemented and an alternative scheme must be provided as a processor extension.
Zifencei:
    Parameter "Zifencei" is 1 on this variant, meaning that the fence.i instruction is implemented (but treated as a NOP by the model). if "Zifencei" is set to 0 then the fence.i instruction is not implemented.
Zicbom:
    Parameter "Zicbom" is 0 on this variant, meaning that code block management instructions are undefined. if "Zicbom" is set to 1 then code block management instructions cbo.clean, cbo.flush and cbo.inval are defined.
    If Zicbom is present, the cache block size is given by parameter "cmomp_bytes". The instructions may cause traps if used illegally but otherwise are NOPs in this model.
Zicbop:
    Parameter "Zicbop" is 0 on this variant, meaning that prefetch instructions are undefined. if "Zicbop" is set to 1 then prefetch instructions prefetch.i, prefetch.r and prefetch.w are defined (but behave as NOPs in this model).
Zicboz:
    Parameter "Zicboz" is 0 on this variant, meaning that the cbo.zero instruction is undefined. if "Zicboz" is set to 1 then the cbo.zero instruction is defined.
    If Zicboz is present, the cache block size is given by parameter "cmoz_bytes".
Smstateen:
    Parameter "Smstateen" is 0 on this variant, meaning that state enable CSRs are undefined. if "Smstateen" is set to 1 then state enable CSRs are defined.
    Within the state enable CSRs, only bit 1 (for Zfinx), bit 57 (for xcontext CSR access), bit 62 (for xenvcfg CSR access) and bit 63 (for lower-level state enable CSR access) are currently implemented.
Load-Reserved/Store-Conditional Locking:
    By default, LR/SC locking is implemented automatically by the model and simulator, with a reservation granule defined by the "lr_sc_grain" parameter. It is also possible to implement locking externally to the model in a platform component, using the "LR_address", "SC_address" and "SC_valid" net ports, as described below.
    The "LR_address" output net port is written by the model with the address used by a load-reserved instruction as it executes. This port should be connected as an input to the external lock management component, which should record the address, and also that an LR/SC transaction is active.
    The "SC_address" output net port is written by the model with the address used by a store-conditional instruction as it executes. This should be connected as an input to the external lock management component, which should compare the address with the previously-recorded load-reserved address, and determine from this (and other implementation-specific constraints) whether the store should succeed. It should then immediately write the Boolean success/fail code to the "SC_valid" input net port of the model. Finally, it should update state to indicate that an LR/SC transaction is no longer active.
    It is also possible to write zero to the "SC_valid" input net port at any time outside the context of a store-conditional instruction, which will mark any active LR/SC transaction as invalid.
    Irrespective of whether LR/SC locking is implemented internally or externally, taking any exception or interrupt or executing exception-return instructions (e.g. MRET) will always mark any active LR/SC transaction as invalid.
    Parameter "amo_aborts_lr_sc" is used to specify whether AMO operations abort any active LR/SC pair. In this variant, "amo_aborts_lr_sc" is 0.
Active Atomic Operation Indication:
    The "AMO_active" output net port is written by the model with a code indicating any current atomic memory operation while the instruction is active. The written codes are:
    0: no atomic instruction active
    1: AMOMIN active
    2: AMOMAX active
    3: AMOMINU active
    4: AMOMAXU active
    5: AMOADD active
    6: AMOXOR active
    7: AMOOR active
    8: AMOAND active
    9: AMOSWAP active
    10: LR active
    11: SC active
Interrupts:
    The "reset" port is an active-high reset input. The processor is halted when "reset" goes high and resumes execution from the reset address specified using the "reset_address" parameter or "reset_addr" port when the signal goes low. The "mcause" register is cleared to zero.
    The "nmi" port is an active-high NMI input. The processor resumes execution from the address specified using the "nmi_address" parameter or "nmi_addr" port when the NMI signal goes high. The "mcause" register is cleared to zero.
    All other interrupt ports are active high. For each implemented privileged execution level, there are by default input ports for software interrupt, timer interrupt and external interrupt; for example, for Machine mode, these are called "MSWInterrupt", "MTimerInterrupt" and "MExternalInterrupt", respectively. When the N extension is implemented, ports are also present for User mode. Parameter "unimp_int_mask" allows the default behavior to be changed to exclude certain interrupt ports. The parameter value is a mask in the same format as the "mip" CSR; any interrupt corresponding to a non-zero bit in this mask will be removed from the processor and read as zero in "mip", "mie" and "mideleg" CSRs (and Supervisor and User mode equivalents if implemented).
    Parameter "external_int_id" can be used to enable extra interrupt ID input ports on each hart. If the parameter is True then when an external interrupt is applied the value on the ID port is sampled and used to fill the Exception Code field in the "mcause" CSR (or the equivalent CSR for other execution levels). For Machine mode, the extra interrupt ID port is called "MExternalInterruptID".
    The "deferint" port is an active-high artifact input that, when written to 1, prevents any pending-and-enabled interrupt being taken (normally, such an interrupt would be taken on the next instruction after it becomes pending-and-enabled). The purpose of this signal is to enable alignment with hardware models in step-and-compare usage.
Debug Mode:
    The model can be configured to implement Debug mode using parameter "debug_mode". This implements features described in Chapter 4 of the RISC-V External Debug Support specification with version specified by parameter "debug_version" (see References). Some aspects of this mode are not defined in the specification because they are implementation-specific; the model provides infrastructure to allow implementation of a Debug Module using a custom harness. Features added are described below.
    Parameter "debug_mode" can be used to specify three different behaviors, as follows:
    1. If set to value "vector", then operations that would cause entry to Debug mode result in the processor jumping to the address specified by the "debug_address" parameter. It will execute at this address, in Debug mode, until a "dret" instruction causes return to non-Debug mode. Any exception generated during this execution will cause a jump to the address specified by the "dexc_address" parameter.
    2. If set to value "interrupt", then operations that would cause entry to Debug mode result in the processor simulation call (e.g. opProcessorSimulate) returning, with a stop reason of OP_SR_INTERRUPT. In this usage scenario, the Debug Module is implemented in the simulation harness.
    3. If set to value "halt", then operations that would cause entry to Debug mode result in the processor halting. Depending on the simulation environment, this might cause a return from the simulation call with a stop reason of OP_SR_HALT, or debug mode might be implemented by another platform component which then restarts the debugged processor again.
Debug State Entry:
    The specification does not define how Debug mode is implemented. In this model, Debug mode is enabled by a Boolean pseudo-register, "DM". When "DM" is True, the processor is in Debug mode. When "DM" is False, mode is defined by "mstatus" in the usual way.
    Entry to Debug mode can be performed in any of these ways:
    1. By writing True to register "DM" (e.g. using opProcessorRegWrite) followed by simulation of at least one cycle (e.g. using opProcessorSimulate), dcsr cause will be reported as trigger;
    2. By writing a 1 then 0 to net "haltreq" (using opNetWrite) followed by simulation of at least one cycle (e.g. using opProcessorSimulate);
    3. By writing a 1 to net "resethaltreq" (using opNetWrite) while the "reset" signal undergoes a negedge transition, followed by simulation of at least one cycle (e.g. using opProcessorSimulate);
    4. By executing an "ebreak" instruction when Debug mode entry for the current processor mode is enabled by dcsr.ebreakm, dcsr.ebreaks or dcsr.ebreaku.
    In all cases, the processor will save required state in "dpc" and "dcsr" and then perform actions described above, depending in the value of the "debug_mode" parameter.
Debug State Exit:
    Exit from Debug mode can be performed in any of these ways:
    1. By writing False to register "DM" (e.g. using opProcessorRegWrite) followed by simulation of at least one cycle (e.g. using opProcessorSimulate);
    2. By executing an "dret" instruction when Debug mode.
    In both cases, the processor will perform the steps described in section 4.6 (Resume) of the Debug specification.
Debug Registers:
    When Debug mode is enabled, registers "dcsr", "dpc", "dscratch0" and "dscratch1" are implemented as described in the specification. These may be manipulated externally by a Debug Module using opProcessorRegRead or opProcessorRegWrite; for example, the Debug Module could write "dcsr" to enable "ebreak" instruction behavior as described above, or read and write "dpc" to emulate stepping over an "ebreak" instruction prior to resumption from Debug mode.
Debug Mode Execution:
    The specification allows execution of code fragments in Debug mode. A Debug Module implementation can cause execution in Debug mode by the following steps:
    1. Write the address of a Program Buffer to the program counter using opProcessorPCSet;
    2. If "debug_mode" is set to "halt", write 0 to pseudo-register "DMStall" (to leave halted state);
    3. If entry to Debug mode was handled by exiting the simulation callback, call opProcessorSimulate or opRootModuleSimulate to resume simulation.
    Debug mode will be re-entered in these cases:
    1. By execution of an "ebreak" instruction; or:
    2. By execution of an instruction that causes an exception.
    In both cases, the processor will either jump to the debug exception address, or return control immediately to the harness, with stopReason of OP_SR_INTERRUPT, or perform a halt, depending on the value of the "debug_mode" parameter.
Debug Single Step:
    When in Debug mode, the processor or harness can cause a single instruction to be executed on return from that mode by setting dcsr.step. After one non-Debug-mode instruction has been executed, control will be returned to the harness. The processor will remain in single-step mode until dcsr.step is cleared.
Debug Event Priorities:
    The model supports two different models for determining which debug exception occurs when multiple debug events are pending:
    1: original mode (when parameter "debug_priority"="original");
    2: modified mode, as described in Debug Specification pull request 693 (when parameter "debug_priority"="PR693"). This mode resolves some anomalous behavior of the original specification.
Debug Ports:
    Port "DM" is an output signal that indicates whether the processor is in Debug mode
    Port "haltreq" is a rising-edge-triggered signal that triggers entry to Debug mode (see above).
    Port "resethaltreq" is a level-sensitive signal that triggers entry to Debug mode after reset (see above).
Debug Mask:
    It is possible to enable model debug messages in various categories. This can be done statically using the "debugflags" parameter, or dynamically using the "debugflags" command. Enabled messages are specified using a bitmask value, as follows:
    Value 0x002: enable debugging of PMP and virtual memory state;
    Value 0x004: enable debugging of interrupt state.
    All other bits in the debug bitmask are reserved and must not be set to non-zero values.
Integration Support:
    This model implements a number of non-architectural pseudo-registers and other features to facilitate integration.
CSR Register External Implementation:
    If parameter "enable_CSR_bus" is True, an artifact 16-bit bus "CSR" is enabled. Slave callbacks installed on this bus can be used to implement modified CSR behavior (use opBusSlaveNew or icmMapExternalMemory, depending on the client API). A CSR with index 0xABC is mapped on the bus at address 0xABC0; as a concrete example, implementing CSR "time" (number 0xC01) externally requires installation of callbacks at address 0xC010 on the CSR bus.
LR/SC Active Address:
    Artifact register "LRSCAddress" shows the active LR/SC lock address. The register holds all-ones if there is no LR/SC operation active or if LR/SC locking is implemented externally as described above.
Limitations:
    Instruction pipelines are not modeled in any way. All instructions are assumed to complete immediately. This means that instruction barrier instructions (e.g. fence.i) are treated as NOPs, with the exception of any Illegal Instruction behavior, which is modeled.
    Caches and write buffers are not modeled in any way. All loads, fetches and stores complete immediately and in order, and are fully synchronous. Data barrier instructions (e.g. fence) are treated as NOPs, with the exception of any Illegal Instruction behavior, which is modeled.
    Real-world timing effects are not modeled: all instructions are assumed to complete in a single cycle.
    Hardware Performance Monitor registers are not implemented and hardwired to zero.
Verification:
    All instructions have been extensively tested by Imperas, using tests generated specifically for this model and also reference tests from https://github.com/riscv/riscv-tests.
    Also reference tests have been used from various sources including:
    https://github.com/riscv/riscv-tests
    https://github.com/ucb-bar/riscv-torture
    The Imperas OVPsim RISC-V models are used in the RISC-V Foundation Compliance Framework as a functional Golden Reference:
    https://github.com/riscv/riscv-compliance
    where the simulated model is used to provide the reference signatures for compliance testing. The Imperas OVPsim RISC-V models are used as reference in both open source and commercial instruction stream test generators for hardware design verification, for example:
    http://valtrix.in/sting from Valtrix
    https://github.com/google/riscv-dv from Google
    The Imperas OVPsim RISC-V models are also used by commercial and open source RISC-V Core RTL developers as a reference to ensure correct functionality of their IP.
References:
    The Model details are based upon the following specifications:
    RISC-V Instruction Set Manual, Volume I: User-Level ISA (User Architecture Version 20191213)
    RISC-V Instruction Set Manual, Volume II: Privileged Architecture (Privileged Architecture Version Ratified-IMFDQC-and-Priv-v1.11)
    RISC-V "B" Bit Manipulation Extension (Bit Manipulation Architecture Version v0.94-20210120)
    RISC-V Core-Local Interrupt Controller (CLIC Version 20180831)
    SiFive S21 Manual v19.05

Model downloadable (needs registration and to be logged in) in package sifive_riscv.model for Windows32 and for Linux32
OVP simulator downloadable (needs registration and to be logged in) in package OVPsim for Windows32 and for Linux32
OVP Download page here.
OVP documentation that provides overview information on processor models is available OVP_Guide_To_Using_Processor_Models.pdf.

Full model specific documentation on the variant S21 is available OVP_Model_Specific_Information_sifive_riscv_S21.pdf.

Configuration


Location: The Fast Processor Model source and object file is found in the installation VLNV tree: sifive.ovpworld.org/processor/riscv/1.0
Processor Endian-ness: This model can be set to either endian-ness (normally by a pin, or the ELF code).
Processor ELF Code: The ELF code for this model is: 0xf3
QuantumLeap Support: The processor model is qualified to run in a QuantumLeap enabled simulator.

TLM Initiator Ports (Bus Ports)

Port TypeNameWidth (bits)Description
masterINSTRUCTION32
masterDATA32

SystemC Signal Ports (Net Ports)

Port TypeNameDescription
hart0_resetinput
hart0_reset_addrinput
hart0_nmiinput
hart0_nmi_causeinput
hart0_nmi_addrinput
hart0_nmiexc_addrinput
hart0_MSWInterruptinput
hart0_MTimerInterruptinput
hart0_MExternalInterruptinput
hart0_CSIPinput
hart0_LocalInterrupt0input
hart0_LocalInterrupt1input
hart0_LocalInterrupt2input
hart0_LocalInterrupt3input
hart0_LocalInterrupt4input
hart0_LocalInterrupt5input
hart0_LocalInterrupt6input
hart0_LocalInterrupt7input
hart0_LocalInterrupt8input
hart0_LocalInterrupt9input
hart0_LocalInterrupt10input
hart0_LocalInterrupt11input
hart0_LocalInterrupt12input
hart0_LocalInterrupt13input
hart0_LocalInterrupt14input
hart0_LocalInterrupt15input
hart0_LocalInterrupt16input
hart0_LocalInterrupt17input
hart0_LocalInterrupt18input
hart0_LocalInterrupt19input
hart0_LocalInterrupt20input
hart0_LocalInterrupt21input
hart0_LocalInterrupt22input
hart0_LocalInterrupt23input
hart0_LocalInterrupt24input
hart0_LocalInterrupt25input
hart0_LocalInterrupt26input
hart0_LocalInterrupt27input
hart0_LocalInterrupt28input
hart0_LocalInterrupt29input
hart0_LocalInterrupt30input
hart0_LocalInterrupt31input
hart0_LocalInterrupt32input
hart0_LocalInterrupt33input
hart0_LocalInterrupt34input
hart0_LocalInterrupt35input
hart0_LocalInterrupt36input
hart0_LocalInterrupt37input
hart0_LocalInterrupt38input
hart0_LocalInterrupt39input
hart0_LocalInterrupt40input
hart0_LocalInterrupt41input
hart0_LocalInterrupt42input
hart0_LocalInterrupt43input
hart0_LocalInterrupt44input
hart0_LocalInterrupt45input
hart0_LocalInterrupt46input
hart0_LocalInterrupt47input
hart0_LocalInterrupt48input
hart0_LocalInterrupt49input
hart0_LocalInterrupt50input
hart0_LocalInterrupt51input
hart0_LocalInterrupt52input
hart0_LocalInterrupt53input
hart0_LocalInterrupt54input
hart0_LocalInterrupt55input
hart0_LocalInterrupt56input
hart0_LocalInterrupt57input
hart0_LocalInterrupt58input
hart0_LocalInterrupt59input
hart0_LocalInterrupt60input
hart0_LocalInterrupt61input
hart0_LocalInterrupt62input
hart0_LocalInterrupt63input
hart0_LocalInterrupt64input
hart0_LocalInterrupt65input
hart0_LocalInterrupt66input
hart0_LocalInterrupt67input
hart0_LocalInterrupt68input
hart0_LocalInterrupt69input
hart0_LocalInterrupt70input
hart0_LocalInterrupt71input
hart0_LocalInterrupt72input
hart0_LocalInterrupt73input
hart0_LocalInterrupt74input
hart0_LocalInterrupt75input
hart0_LocalInterrupt76input
hart0_LocalInterrupt77input
hart0_LocalInterrupt78input
hart0_LocalInterrupt79input
hart0_LocalInterrupt80input
hart0_LocalInterrupt81input
hart0_LocalInterrupt82input
hart0_LocalInterrupt83input
hart0_LocalInterrupt84input
hart0_LocalInterrupt85input
hart0_LocalInterrupt86input
hart0_LocalInterrupt87input
hart0_LocalInterrupt88input
hart0_LocalInterrupt89input
hart0_LocalInterrupt90input
hart0_LocalInterrupt91input
hart0_LocalInterrupt92input
hart0_LocalInterrupt93input
hart0_LocalInterrupt94input
hart0_LocalInterrupt95input
hart0_LocalInterrupt96input
hart0_LocalInterrupt97input
hart0_LocalInterrupt98input
hart0_LocalInterrupt99input
hart0_LocalInterrupt100input
hart0_LocalInterrupt101input
hart0_LocalInterrupt102input
hart0_LocalInterrupt103input
hart0_LocalInterrupt104input
hart0_LocalInterrupt105input
hart0_LocalInterrupt106input
hart0_LocalInterrupt107input
hart0_LocalInterrupt108input
hart0_LocalInterrupt109input
hart0_LocalInterrupt110input
hart0_LocalInterrupt111input
hart0_LocalInterrupt112input
hart0_LocalInterrupt113input
hart0_LocalInterrupt114input
hart0_LocalInterrupt115input
hart0_LocalInterrupt116input
hart0_LocalInterrupt117input
hart0_LocalInterrupt118input
hart0_LocalInterrupt119input
hart0_LocalInterrupt120input
hart0_LocalInterrupt121input
hart0_LocalInterrupt122input
hart0_LocalInterrupt123input
hart0_LocalInterrupt124input
hart0_LocalInterrupt125input
hart0_LocalInterrupt126input
hart0_irq_ack_ooutput
hart0_irq_id_ooutput
hart0_sec_lvl_ooutput
hart0_LR_addressoutput
hart0_SC_addressoutput
hart0_SC_validinput
hart0_AMO_activeoutput
hart0_deferintinput

No FIFO Ports in S21.


Exceptions

NameCodeDescription
InstructionAddressMisaligned0
InstructionAccessFault1
IllegalInstruction2
Breakpoint3
LoadAddressMisaligned4
LoadAccessFault5
StoreAMOAddressMisaligned6
StoreAMOAccessFault7
EnvironmentCallFromUMode8
EnvironmentCallFromMMode11
InstructionPageFault12
LoadPageFault13
StoreAMOPageFault15
MSWInterrupt67
MTimerInterrupt71
MExternalInterrupt75
CSIP76
LocalInterrupt080
LocalInterrupt181
LocalInterrupt282
LocalInterrupt383
LocalInterrupt484
LocalInterrupt585
LocalInterrupt686
LocalInterrupt787
LocalInterrupt888
LocalInterrupt989
LocalInterrupt1090
LocalInterrupt1191
LocalInterrupt1292
LocalInterrupt1393
LocalInterrupt1494
LocalInterrupt1595
LocalInterrupt1696
LocalInterrupt1797
LocalInterrupt1898
LocalInterrupt1999
LocalInterrupt20100
LocalInterrupt21101
LocalInterrupt22102
LocalInterrupt23103
LocalInterrupt24104
LocalInterrupt25105
LocalInterrupt26106
LocalInterrupt27107
LocalInterrupt28108
LocalInterrupt29109
LocalInterrupt30110
LocalInterrupt31111
LocalInterrupt32112
LocalInterrupt33113
LocalInterrupt34114
LocalInterrupt35115
LocalInterrupt36116
LocalInterrupt37117
LocalInterrupt38118
LocalInterrupt39119
LocalInterrupt40120
LocalInterrupt41121
LocalInterrupt42122
LocalInterrupt43123
LocalInterrupt44124
LocalInterrupt45125
LocalInterrupt46126
LocalInterrupt47127
LocalInterrupt48128
LocalInterrupt49129
LocalInterrupt50130
LocalInterrupt51131
LocalInterrupt52132
LocalInterrupt53133
LocalInterrupt54134
LocalInterrupt55135
LocalInterrupt56136
LocalInterrupt57137
LocalInterrupt58138
LocalInterrupt59139
LocalInterrupt60140
LocalInterrupt61141
LocalInterrupt62142
LocalInterrupt63143
LocalInterrupt64144
LocalInterrupt65145
LocalInterrupt66146
LocalInterrupt67147
LocalInterrupt68148
LocalInterrupt69149
LocalInterrupt70150
LocalInterrupt71151
LocalInterrupt72152
LocalInterrupt73153
LocalInterrupt74154
LocalInterrupt75155
LocalInterrupt76156
LocalInterrupt77157
LocalInterrupt78158
LocalInterrupt79159
LocalInterrupt80160
LocalInterrupt81161
LocalInterrupt82162
LocalInterrupt83163
LocalInterrupt84164
LocalInterrupt85165
LocalInterrupt86166
LocalInterrupt87167
LocalInterrupt88168
LocalInterrupt89169
LocalInterrupt90170
LocalInterrupt91171
LocalInterrupt92172
LocalInterrupt93173
LocalInterrupt94174
LocalInterrupt95175
LocalInterrupt96176
LocalInterrupt97177
LocalInterrupt98178
LocalInterrupt99179
LocalInterrupt100180
LocalInterrupt101181
LocalInterrupt102182
LocalInterrupt103183
LocalInterrupt104184
LocalInterrupt105185
LocalInterrupt106186
LocalInterrupt107187
LocalInterrupt108188
LocalInterrupt109189
LocalInterrupt110190
LocalInterrupt111191
LocalInterrupt112192
LocalInterrupt113193
LocalInterrupt114194
LocalInterrupt115195
LocalInterrupt116196
LocalInterrupt117197
LocalInterrupt118198
LocalInterrupt119199
LocalInterrupt120200
LocalInterrupt121201
LocalInterrupt122202
LocalInterrupt123203
LocalInterrupt124204
LocalInterrupt125205
LocalInterrupt126206

Execution Modes

ModeCodeDescription
User0
Machine3

More Detailed Information

The S21 OVP Fast Processor Model also has parameters, model commands, and many registers.
The model may also have hierarchy or be multicore and have other attributes and capabilities.
To see this information, please have a look at the model variant specific documents.
Click here to see the detailed document OVP_Model_Specific_Information_sifive_riscv_S21.pdf.

Other Sites/Pages with similar information

Information on the S21 OVP Fast Processor Model can also be found on other web sites:
www.imperas.com has more information on the model library.



SiFiveProcessors
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