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SifiveDDRCTL



OVP Peripheral Model: SifiveDDRCTL



Model Specific Information

This page provides introductory usage information for an Imperas OVP peripheral behavioral model. The page is split into sections providing specific information for this peripheral, including any ports for connecting into a platform, registers, other component parts, and configuration options and general information for peripheral modeling with Imperas OVP.

Description

DDR Controller Register Block for SiFive FU540 chip

Licensing

Open Source Apache 2.0

Reference

SiFive Freedom U540-C000 Manual FU540-C000-v1.0.pdf (https://www.sifive.com/documentation/chips/freedom-u540-c000-manual)

Limitations

Register only model. Register address space modeled as RAM except for registers that require write masks or reset values.

Location

The DDRCTL peripheral model is located in an Imperas/OVP installation at the VLNV: sifive.ovpworld.org / peripheral / DDRCTL / 1.0.



Bus Slave Ports

This model has the following bus slave ports:

Bus Slave Port: CONTROL

Table : Bus Slave Port: CONTROL

NameSize (bytes)Must Be ConnectedDescription
CONTROL0x4000T (True)

Table 1: Bus Slave Port: CONTROL Registers:

NameOffsetWidth (bits)DescriptionR/Wis Volatile
REGS_reg330x8432

Bus Slave Port: BLOCKER

Table 2: Bus Slave Port: BLOCKER

NameSize (bytes)Must Be ConnectedDescription
BLOCKER0x8T (True)


No address blocks have been defined for this slave port.



Platforms that use this peripheral component

Peripheral components can be used in many different platforms, including those developed by Imperas or by other users of OVP. You can use this peripheral in your own platforms.

Table 3: Publicly available platforms using peripheral 'DDRCTL'

Platform NameVendor
FU540sifive.ovpworld.org



SiFivePeripherals
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