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SifiveGpio



OVP Peripheral Model: SifiveGpio



Model Specific Information

This page provides introductory usage information for an Imperas OVP peripheral behavioral model. The page is split into sections providing specific information for this peripheral, including any ports for connecting into a platform, registers, other component parts, and configuration options and general information for peripheral modeling with Imperas OVP.

Limitations

This model implements only the registers for generation of input or output data values.

Licensing

Open Source Apache 2.0

Description

Included is the visualization of LED and SW connectivity.

SiFive coreip-s51-arty GPIO Registers (gpio)

Reference

SiFive Freedom E SDK coreip-s51-arty Board Support Package details.

Location

The gpio peripheral model is located in an Imperas/OVP installation at the VLNV: sifive.ovpworld.org / peripheral / gpio / 1.0.



Peripheral Instance Parameters

This model accepts the following parameters:

Table : Peripheral Parameters

NameTypeDescription
recordstringRecord external events into this file
httpvisdirstringSpecify an alternative directory for visualization data
httpvisportnumuns32Specify the HTTP port number
replaystringReplay external events from this file



Net Ports

This model has the following net ports:

Table 1: Net Ports

NameTypeMust Be ConnectedDescription
intSW1outputF (False)
intBTN0outputF (False)
intSW0outputF (False)
gpiooutoutputF (False)
gpioininputF (False)
intOut15outputF (False)
intOut14outputF (False)
intOut13outputF (False)
intOut12outputF (False)
intOut11outputF (False)
intOut10outputF (False)
intOut9outputF (False)
intOut8outputF (False)
intOut7outputF (False)
intOut6outputF (False)
intOut5outputF (False)
intOut4outputF (False)
intOut3outputF (False)
intOut2outputF (False)
intOut1outputF (False)
intOut0outputF (False)
resetNetinputF (False)
intBTN1outputF (False)
intSW2outputF (False)
intBTN2outputF (False)
intSW3outputF (False)
intBTN3outputF (False)



Bus Slave Ports

This model has the following bus slave ports:

Bus Slave Port: bport1

Table 2: Bus Slave Port: bport1

NameSize (bytes)Must Be ConnectedDescription
bport10x1000T (True)

Table 3: Bus Slave Port: bport1 Registers:

NameOffsetWidth (bits)DescriptionR/Wis Volatile
REG_LOW_IP0x3432Low level interrupt pending
REG_LOW_IE0x3032Low level interupt enable
REG_HIGH_IP0x2c32High level interrupt pending
REG_HIGH_IE0x2832High level edge interupt enable
REG_FALL_IP0x2432Falling interrupt pending
REG_FALL_IE0x2032Falling edge interupt enable
REG_RISE_IP0x1c32Rising interrupt pending
REG_RISE_IE0x1832Rising edge interupt enable
REG_DS0x1432Pin Drive Strength
REG_PUE0x1032Internal pull-up enabled
REG_PORT0xc32Output Port Value
REG_OUTPUT_EN0x832Enable Output bits
REG_INPUT_EN0x432Enable Input bits
REG_VALUE0x032Pin Value
REG_IOF_EN0x3832H/W I/O Function enable
REG_IOF_SEL0x3c32H/W I/O Function Select
REG_OUT_XOR0x4032Output XOR (invert)



Platforms that use this peripheral component

Peripheral components can be used in many different platforms, including those developed by Imperas or by other users of OVP. You can use this peripheral in your own platforms.

Table 4: Publicly available platforms using peripheral 'gpio'

Platform NameVendor
coreip-s51-artysifive.ovpworld.org



SiFivePeripherals
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