OVP Peripheral Model: SifiveGpio
Model Specific Information
This page provides introductory usage information for an Imperas OVP peripheral behavioral model.
The page is split into sections providing specific information for this peripheral,
including any ports for connecting into a platform, registers, other component parts, and configuration options and general information for peripheral modeling with Imperas OVP.
Description
SiFive coreip-s51-arty GPIO Registers (gpio)
Licensing
Open Source Apache 2.0
Limitations
This model implements only the registers for generation of input or output data values.
Reference
SiFive Freedom E SDK coreip-s51-arty Board Support Package details.
Location
The gpio peripheral model is located in an Imperas/OVP installation at the VLNV: sifive.ovpworld.org / peripheral / gpio / 1.0.
Peripheral Instance Parameters
This model accepts the following parameters:
Table : Peripheral Parameters
Name | Type | Description |
---|
httpvisportnum | uns32 | Specify the HTTP port number |
httpvisdir | string | Specify an alternative directory for visualization data |
record | string | Record external events into this file |
replay | string | Replay external events from this file |
Net Ports
This model has the following net ports:
Table 1: Net Ports
Name | Type | Must Be Connected | Description |
---|
resetNet | input | F (False) | |
intOut0 | output | F (False) | |
intOut1 | output | F (False) | |
intOut2 | output | F (False) | |
intOut3 | output | F (False) | |
intOut4 | output | F (False) | |
intOut5 | output | F (False) | |
intOut6 | output | F (False) | |
intOut7 | output | F (False) | |
intOut8 | output | F (False) | |
intOut9 | output | F (False) | |
intOut10 | output | F (False) | |
intOut11 | output | F (False) | |
intOut12 | output | F (False) | |
intOut13 | output | F (False) | |
intOut14 | output | F (False) | |
intOut15 | output | F (False) | |
gpios0 | inout | F (False) | |
gpios1 | inout | F (False) | |
gpios2 | inout | F (False) | |
gpios3 | inout | F (False) | |
gpios4 | inout | F (False) | |
gpios5 | inout | F (False) | |
gpios6 | inout | F (False) | |
gpios7 | inout | F (False) | |
gpios8 | inout | F (False) | |
gpios9 | inout | F (False) | |
gpios10 | inout | F (False) | |
gpios11 | inout | F (False) | |
gpios12 | inout | F (False) | |
gpios13 | inout | F (False) | |
gpios14 | inout | F (False) | |
gpios15 | inout | F (False) | |
Bus Slave Ports
This model has the following bus slave ports:
Bus Slave Port: bport1
Table 2: Bus Slave Port: bport1
Name | Size (bytes) | Must Be Connected | Description |
---|
bport1 | 0x1000 | T (True) | |
Table 3: Bus Slave Port: bport1 Registers:
Name | Offset | Width (bits) | Description | R/W | is Volatile |
---|
REG_VALUE | 0x0 | 32 | Pin Value | | |
REG_INPUT_EN | 0x4 | 32 | Enable Input bits | | |
REG_OUTPUT_EN | 0x8 | 32 | Enable Output bits | | |
REG_PORT | 0xc | 32 | Output Port Value | | |
REG_PUE | 0x10 | 32 | Internal pull-up enabled | | |
REG_DS | 0x14 | 32 | Pin Drive Strength | | |
REG_RISE_IE | 0x18 | 32 | Rising edge interrupt enable | | |
REG_RISE_IP | 0x1c | 32 | Rising interrupt pending | | |
REG_FALL_IE | 0x20 | 32 | Falling edge interrupt enable | | |
REG_FALL_IP | 0x24 | 32 | Falling interrupt pending | | |
REG_HIGH_IE | 0x28 | 32 | High level edge interrupt enable | | |
REG_HIGH_IP | 0x2c | 32 | High level interrupt pending | | |
REG_LOW_IE | 0x30 | 32 | Low level interrupt enable | | |
REG_LOW_IP | 0x34 | 32 | Low level interrupt pending | | |
REG_IOF_EN | 0x38 | 32 | H/W I/O Function enable | | |
REG_IOF_SEL | 0x3c | 32 | H/W I/O Function Select | | |
REG_OUT_XOR | 0x40 | 32 | Output XOR (invert) | | |
Platforms that use this peripheral component
Peripheral components can be used in many different platforms, including those developed by Imperas or by other users of OVP. You can use this peripheral in your own platforms.
Table 4: Publicly available platforms using peripheral 'gpio'