OVP Peripheral Model: SifivePLIC
Model Specific Information
This page provides introductory usage information for an Imperas OVP peripheral behavioral model.
The page is split into sections providing specific information for this peripheral,
including any ports for connecting into a platform, registers, other component parts, and configuration options and general information for peripheral modeling with Imperas OVP.
Licensing
Open Source Apache 2.0
Description
SiFive PLIC Interrupt Controller
Use parameters to configure specific implementation.
Reference
Various SiFive Core Complex manuals, e.g. SiFive E31 Core Complex Manual 31G2.01.00 (https://sifive.cdn.prismic.io/sifive/c29f9c69-5254-4f9a-9e18-24ea73f34e81_e31_core_complex_manual_21G2.pdf)
Location
The PLIC peripheral model is located in an Imperas/OVP installation at the VLNV: sifive.ovpworld.org / peripheral / PLIC / 1.0.
Peripheral Instance Parameters
This model accepts the following parameters:
Table : Peripheral Parameters
Name | Type | Description |
---|
num_sources | uns32 | Number of Input Interrupt Sources |
num_targets | uns32 | Number of Output Interrupt Targets, Hart/Context |
num_priorities | uns32 | Number of Priority levels |
priority_base | uns32 | Base Address offset for Priority Registers |
pending_base | uns32 | Base Address offset for Pending Registers |
enable_base | uns32 | Base Address offset for Enable Registers |
enable_stride | uns32 | Stride size for Enable Register Block |
context_base | uns32 | Base Address offset for Context Registers, Threshold/Claim |
context_stride | uns32 | Stride size for Context Register Block |
Net Ports
This model has the following net ports:
Table 1: Net Ports
Name | Type | Must Be Connected | Description |
---|
reset | input | F (False) | Reset signal |
irqS1 | input | F (False) | |
irqT0 | output | F (False) | |
Bus Slave Ports
This model has the following bus slave ports:
Bus Slave Port: port0
Table 2: Bus Slave Port: port0
Name | Size (bytes) | Must Be Connected | Description |
---|
port0 | 0x400000 | F (False) | |
Table 3: Bus Slave Port: port0 Registers:
Name | Offset | Width (bits) | Description | R/W | is Volatile |
---|
Priority1 | 0x4 | 32 | Priority of Input Interrupt Source 1 | | |
Pending0 | 0x1000 | 32 | Pending Interrupt Register for Interrupts 31 down to 0 | | |
Target0_Enable0 | 0x2000 | 32 | Target 0: Enable Register for Interrupts 31 down to 0 | | |
Target0_Threshold | 0x200000 | 32 | Target 0 Priority Threshold | | |
Target0_Claim | 0x200004 | 32 | Target 0 Claim for Source | | |
disablePlicClockGateFeature | 0x1ff000 | 32 | SiFive PLIC Clock Gate Disable Register | | |
Platforms that use this peripheral component
Peripheral components can be used in many different platforms, including those developed by Imperas or by other users of OVP. You can use this peripheral in your own platforms.
Table 4: Publicly available platforms using peripheral 'PLIC'