LIBRARY | COMPANIES | PLATFORMS | PROCESSORS | PERIPHERALS
TensilicaDiamond
You can use Tensilica processor models within OVP simulations. This is accomplished by 'wrapping' the Tensilica processor model with an 'integration adaptor' to encapsulate it and make it appear to an OVP platform as a normal OVP processor model.
Tensilica Diamond Core ISS Encapsulation Example
There is an encapsulation of Tensilica Diamond Core processors available for use in OVP. Usage of this integration is shown in the normal OVPsim installer download by an example platform:
Some general details about this example platform and specific details of the encapsulation are given here.
Prerequisites
In order to use the encapsulation, you must have available and installed the Tensilica Turbo Xim fast functional simulator. In order to create applications, you will also need to install the Tensilica compiler toolchain. Visit www.tensilica.com∞ for more information.
Example details
See the file README.txt in the example directory for a description of the encapsulation example.
Encapsulation Details
The Tensilica Turbo Xim fast functional simulator is encapsulated by an OVP wrapper. The encapsulation can support any processor type supported by the Tensilica simulator - the specific variant is defined by the processor type string when a processor instance is created. The example platform contains two instances of the DC_570T core (the variant is set in the Makefile). Consult the Tensilica documentation for a full list of processor variants supported by Turbo Xim.
OVP FIFO objects can be used to connect Tensilica processors if required. In the example platform, a single 8-entry FIFO is used to connect the two DC_570T cores, and a text message is passed between the cores using the FIFO.
Restrictions (June 08)
The encapsulation doesn't currently support the Imperas Multi-Core Debugger. In the current release the encapsulated Tensilica processor can be debugged with GDB. This restriction will hopefully be addressed with the next release of the Tensilica Turbo Xim simulator.
For more information about this encapsulation - please contact us at info[at]ovpworld.org or via the www.ovpworld.org/forum∞.
Component Description for TensilicaDiamond/DC_108mini.xml
Component Description for TensilicaDiamond/DC_108mini_2.xml
Component Description for TensilicaDiamond/DC_108mini_be.xml
Component Description for TensilicaDiamond/DC_212GP.xml
Component Description for TensilicaDiamond/DC_232L.xml
Component Description for TensilicaDiamond/DC_330HiFi.xml
Component Description for TensilicaDiamond/DC_545CK.xml
Component Description for TensilicaDiamond/DC_570T.xml
Component Description for TensilicaDiamond/DC_570T_2.xml
Component Description for TensilicaDiamond/DC_570T_be.xml
Component Description for TensilicaDiamond/DC_B_106micro.xml
Component Description for TensilicaDiamond/DC_B_108mini.xml
Component Description for TensilicaDiamond/DC_B_212GP.xml
Component Description for TensilicaDiamond/DC_B_232L.xml
Component Description for TensilicaDiamond/DC_B_330HiFi.xml
Component Description for TensilicaDiamond/DC_B_545CK.xml
Component Description for TensilicaDiamond/DC_B_570T.xml
Component Description for TensilicaDiamond/DC_B_570T_2.xml
Component Description for TensilicaDiamond/diamondCore.model.xml
Component Description for TensilicaDiamond/tensilica.model.xml
CategoryProcessor ImperasPage TensilicaPage
You can use Tensilica processor models within OVP simulations. This is accomplished by 'wrapping' the Tensilica processor model with an 'integration adaptor' to encapsulate it and make it appear to an OVP platform as a normal OVP processor model.
 | DOWNLOAD OVP Tensilica ISS Integration Adapter TensilicaDiamond.zip / 28.63 KB |
Tensilica Diamond Core ISS Encapsulation Example
There is an encapsulation of Tensilica Diamond Core processors available for use in OVP. Usage of this integration is shown in the normal OVPsim installer download by an example platform:
Examples/Vendors/Tensilica/DC_570Tx2
Prerequisites
In order to use the encapsulation, you must have available and installed the Tensilica Turbo Xim fast functional simulator. In order to create applications, you will also need to install the Tensilica compiler toolchain. Visit www.tensilica.com∞ for more information.
Example details
See the file README.txt in the example directory for a description of the encapsulation example.
Encapsulation Details
The Tensilica Turbo Xim fast functional simulator is encapsulated by an OVP wrapper. The encapsulation can support any processor type supported by the Tensilica simulator - the specific variant is defined by the processor type string when a processor instance is created. The example platform contains two instances of the DC_570T core (the variant is set in the Makefile). Consult the Tensilica documentation for a full list of processor variants supported by Turbo Xim.
OVP FIFO objects can be used to connect Tensilica processors if required. In the example platform, a single 8-entry FIFO is used to connect the two DC_570T cores, and a text message is passed between the cores using the FIFO.
Restrictions (June 08)
The encapsulation doesn't currently support the Imperas Multi-Core Debugger. In the current release the encapsulated Tensilica processor can be debugged with GDB. This restriction will hopefully be addressed with the next release of the Tensilica Turbo Xim simulator.
For more information about this encapsulation - please contact us at info[at]ovpworld.org or via the www.ovpworld.org/forum∞.
| Attachment | Size | Date Added | |
| DC_108mini.xml | 1.05 KB | 11/22/2016 5:52 pm | |
| DC_108mini_2.xml | 1.84 KB | 11/22/2016 5:52 pm | |
| DC_108mini_be.xml | 1.07 KB | 11/22/2016 5:52 pm | |
| DC_212GP.xml | 4.32 KB | 11/22/2016 5:52 pm | |
| DC_232L.xml | 4.32 KB | 11/22/2016 5:52 pm | |
| DC_330HiFi.xml | 4.33 KB | 11/22/2016 5:52 pm | |
| DC_545CK.xml | 4.32 KB | 11/22/2016 5:52 pm | |
| DC_570T.xml | 1.07 KB | 11/22/2016 5:52 pm | |
| DC_570T_2.xml | 2.25 KB | 11/22/2016 5:52 pm | |
| DC_570T_be.xml | 1.09 KB | 11/22/2016 5:52 pm | |
| DC_B_106micro.xml | 4.35 KB | 11/22/2016 5:52 pm | |
| DC_B_108mini.xml | 4.35 KB | 11/22/2016 5:52 pm | |
| DC_B_212GP.xml | 4.34 KB | 11/22/2016 5:52 pm | |
| DC_B_232L.xml | 4.34 KB | 11/22/2016 5:52 pm | |
| DC_B_330HiFi.xml | 4.35 KB | 11/22/2016 5:52 pm | |
| DC_B_545CK.xml | 4.5 KB | 11/22/2016 5:52 pm | |
| DC_B_570T.xml | 4.5 KB | 11/22/2016 5:52 pm | |
| DC_B_570T_2.xml | 2.26 KB | 11/22/2016 5:52 pm | |
| diamondCore.model.xml | 4.48 KB | 11/22/2016 5:52 pm | |
| tensilica.model.xml | 4.47 KB | 11/22/2016 5:52 pm | |
| TensilicaDiamond.zip | 28.63 KB | 11/22/2016 5:52 pm | |
HW | DC_108mini |
PROCESSORINSTANCE | cpuA |
| ID | 0 |
| TRAP | 1 |
VLNVREFERENCE | DC_108mini |
BUSMASTERPORTCONNECTION | INSTRUCTION |
| CONNECTION | bus1 |
| HIADDRESS | 0xffffffff |
| LOADDRESS | 0x0 |
BUSMASTERPORTCONNECTION | DATA |
| CONNECTION | bus1 |
| HIADDRESS | 0xffffffff |
| LOADDRESS | 0x0 |
BUS | bus1 |
| ADDRESSWIDTH | 32 |
MEMORYINSTANCE | ram1 |
VLNVREFERENCE | ram |
BUSSLAVEPORTCONNECTION | sp1 |
| CONNECTION | bus1 |
| HIADDRESS | 0xffffffff |
| LOADDRESS | 0x0 |
FILEVERSION | _version |
| MAJOR | 1 |
| MINOR | 0 |
HW | DC_108mini2 |
PROCESSORINSTANCE | cpuA |
| ID | 0 |
| TRAP | 1 |
VLNVREFERENCE | DC_108mini |
BUSMASTERPORTCONNECTION | INSTRUCTION |
| CONNECTION | bus1 |
| HIADDRESS | 0xffffffff |
| LOADDRESS | 0x0 |
BUSMASTERPORTCONNECTION | DATA |
| CONNECTION | bus1 |
| HIADDRESS | 0xffffffff |
| LOADDRESS | 0x0 |
BUS | bus1 |
| ADDRESSWIDTH | 32 |
MEMORYINSTANCE | ram1 |
VLNVREFERENCE | ram |
BUSSLAVEPORTCONNECTION | sp1 |
| CONNECTION | bus1 |
| HIADDRESS | 0xffffffff |
| LOADDRESS | 0x0 |
PROCESSORINSTANCE | cpuB |
| ID | 1 |
| TRAP | 1 |
VLNVREFERENCE | DC_108mini |
BUSMASTERPORTCONNECTION | INSTRUCTION |
| CONNECTION | bus2 |
| HIADDRESS | 0xffffffff |
| LOADDRESS | 0x0 |
BUSMASTERPORTCONNECTION | DATA |
| CONNECTION | bus2 |
| HIADDRESS | 0xffffffff |
| LOADDRESS | 0x0 |
BUS | bus2 |
| ADDRESSWIDTH | 32 |
MEMORYINSTANCE | ram2 |
VLNVREFERENCE | ram |
BUSSLAVEPORTCONNECTION | sp1 |
| CONNECTION | bus2 |
| HIADDRESS | 0xffffffff |
| LOADDRESS | 0x0 |
FILEVERSION | _version |
| MAJOR | 1 |
| MINOR | 0 |
HW | DC_108mini_be |
PROCESSORINSTANCE | cpuA |
| ID | 0 |
| TRAP | 1 |
| ENDIAN | big |
VLNVREFERENCE | DC_108mini |
BUSMASTERPORTCONNECTION | INSTRUCTION |
| CONNECTION | bus1 |
| HIADDRESS | 0xffffffff |
| LOADDRESS | 0x0 |
BUSMASTERPORTCONNECTION | DATA |
| CONNECTION | bus1 |
| HIADDRESS | 0xffffffff |
| LOADDRESS | 0x0 |
BUS | bus1 |
| ADDRESSWIDTH | 32 |
MEMORYINSTANCE | ram1 |
VLNVREFERENCE | ram |
BUSSLAVEPORTCONNECTION | sp1 |
| CONNECTION | bus1 |
| HIADDRESS | 0xffffffff |
| LOADDRESS | 0x0 |
FILEVERSION | _version |
| MAJOR | 1 |
| MINOR | 0 |
PROCESSOR | DC_212GP |
| ENDIAN | either |
| ELFCODE | 94 |
| ATTRIBUTETABLE | modelAttrs |
| LIBRARY | processor |
| LOADPHYSICAL | F |
| IMAGEFILE | model |
| GDBPATH | ${XTENSA_BIN}/xt-gdb |
| GDBFLAGS | --xtensa-core=DC_212GP |
| SIGNATURE | 0 |
| VENDOR | ovpworld.org |
| VERSION | 1.0 |
| License | Open Source Apache 2.0 |
| Description | Tensilica DC_212GP ISS integration. |
| Limitations | Does not currently support debug. |
BUSMASTERPORT | INSTRUCTION |
| ADDRESSWIDTH | 32 |
| MUSTBECONNECTED | F |
BUSMASTERPORT | DATA |
| ADDRESSWIDTH | 32 |
| MUSTBECONNECTED | F |
REGISTERS | registers |
REGISTER | mr0 |
| WIDTH | 32 |
| TYPE | 4 |
| READONLY | T |
REGISTER | mr1 |
| WIDTH | 32 |
| TYPE | 2 |
| READONLY | F |
REGISTER | mr2 |
| WIDTH | 32 |
| TYPE | 3 |
| READONLY | F |
REGISTER | mr3 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | lbeg |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | lend |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | lcount |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | acclo |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | acchi |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | sar |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | litbaddr |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ps |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | scompare1 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | expstate |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | pc |
| WIDTH | 32 |
| TYPE | 1 |
| READONLY | F |
REGISTER | ar0 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar1 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar2 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar3 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar4 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar5 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar6 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar7 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar8 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar9 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar10 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar11 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar12 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar13 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar14 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar15 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | windowbase |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | windowstart |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
FILEVERSION | _version |
| MAJOR | 1 |
| MINOR | 0 |
PROCESSOR | DC_232L |
| ENDIAN | either |
| ELFCODE | 94 |
| ATTRIBUTETABLE | modelAttrs |
| LIBRARY | processor |
| LOADPHYSICAL | F |
| IMAGEFILE | model |
| GDBPATH | ${XTENSA_BIN}/xt-gdb |
| GDBFLAGS | --xtensa-core=DC_232L |
| SIGNATURE | 0 |
| VENDOR | ovpworld.org |
| VERSION | 1.0 |
| License | Open Source Apache 2.0 |
| Description | Tensilica DC_232L ISS integration. |
| Limitations | Does not currently support debug. |
BUSMASTERPORT | INSTRUCTION |
| ADDRESSWIDTH | 32 |
| MUSTBECONNECTED | F |
BUSMASTERPORT | DATA |
| ADDRESSWIDTH | 32 |
| MUSTBECONNECTED | F |
REGISTERS | registers |
REGISTER | mr0 |
| WIDTH | 32 |
| TYPE | 4 |
| READONLY | T |
REGISTER | mr1 |
| WIDTH | 32 |
| TYPE | 2 |
| READONLY | F |
REGISTER | mr2 |
| WIDTH | 32 |
| TYPE | 3 |
| READONLY | F |
REGISTER | mr3 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | lbeg |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | lend |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | lcount |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | acclo |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | acchi |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | sar |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | litbaddr |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ps |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | scompare1 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | expstate |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | pc |
| WIDTH | 32 |
| TYPE | 1 |
| READONLY | F |
REGISTER | ar0 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar1 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar2 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar3 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar4 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar5 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar6 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar7 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar8 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar9 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar10 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar11 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar12 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar13 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar14 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar15 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | windowbase |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | windowstart |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
FILEVERSION | _version |
| MAJOR | 1 |
| MINOR | 0 |
PROCESSOR | DC_330HiFi |
| ENDIAN | either |
| ELFCODE | 94 |
| ATTRIBUTETABLE | modelAttrs |
| LIBRARY | processor |
| LOADPHYSICAL | F |
| IMAGEFILE | model |
| GDBPATH | ${XTENSA_BIN}/xt-gdb |
| GDBFLAGS | --xtensa-core=DC_330HiFi |
| SIGNATURE | 0 |
| VENDOR | ovpworld.org |
| VERSION | 1.0 |
| License | Open Source Apache 2.0 |
| Description | Tensilica DC_330HiFi ISS integration. |
| Limitations | Does not currently support debug. |
BUSMASTERPORT | INSTRUCTION |
| ADDRESSWIDTH | 32 |
| MUSTBECONNECTED | F |
BUSMASTERPORT | DATA |
| ADDRESSWIDTH | 32 |
| MUSTBECONNECTED | F |
REGISTERS | registers |
REGISTER | mr0 |
| WIDTH | 32 |
| TYPE | 4 |
| READONLY | T |
REGISTER | mr1 |
| WIDTH | 32 |
| TYPE | 2 |
| READONLY | F |
REGISTER | mr2 |
| WIDTH | 32 |
| TYPE | 3 |
| READONLY | F |
REGISTER | mr3 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | lbeg |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | lend |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | lcount |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | acclo |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | acchi |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | sar |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | litbaddr |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ps |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | scompare1 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | expstate |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | pc |
| WIDTH | 32 |
| TYPE | 1 |
| READONLY | F |
REGISTER | ar0 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar1 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar2 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar3 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar4 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar5 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar6 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar7 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar8 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar9 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar10 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar11 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar12 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar13 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar14 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar15 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | windowbase |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | windowstart |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
FILEVERSION | _version |
| MAJOR | 1 |
| MINOR | 0 |
PROCESSOR | DC_545CK |
| ENDIAN | either |
| ELFCODE | 94 |
| ATTRIBUTETABLE | modelAttrs |
| LIBRARY | processor |
| LOADPHYSICAL | F |
| IMAGEFILE | model |
| GDBPATH | ${XTENSA_BIN}/xt-gdb |
| GDBFLAGS | --xtensa-core=DC_545CK |
| SIGNATURE | 0 |
| VENDOR | ovpworld.org |
| VERSION | 1.0 |
| License | Open Source Apache 2.0 |
| Description | Tensilica DC_545CK ISS integration. |
| Limitations | Does not currently support debug. |
BUSMASTERPORT | INSTRUCTION |
| ADDRESSWIDTH | 32 |
| MUSTBECONNECTED | F |
BUSMASTERPORT | DATA |
| ADDRESSWIDTH | 32 |
| MUSTBECONNECTED | F |
REGISTERS | registers |
REGISTER | mr0 |
| WIDTH | 32 |
| TYPE | 4 |
| READONLY | T |
REGISTER | mr1 |
| WIDTH | 32 |
| TYPE | 2 |
| READONLY | F |
REGISTER | mr2 |
| WIDTH | 32 |
| TYPE | 3 |
| READONLY | F |
REGISTER | mr3 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | lbeg |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | lend |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | lcount |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | acclo |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | acchi |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | sar |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | litbaddr |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ps |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | scompare1 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | expstate |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | pc |
| WIDTH | 32 |
| TYPE | 1 |
| READONLY | F |
REGISTER | ar0 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar1 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar2 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar3 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar4 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar5 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar6 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar7 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar8 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar9 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar10 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar11 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar12 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar13 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar14 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar15 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | windowbase |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | windowstart |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
FILEVERSION | _version |
| MAJOR | 1 |
| MINOR | 0 |
HW | DC_570T |
PROCESSORINSTANCE | cpuA |
| ID | 0 |
| TRAP | 1 |
| ENDIAN | little |
VLNVREFERENCE | DC_570T |
BUSMASTERPORTCONNECTION | INSTRUCTION |
| CONNECTION | bus1 |
| HIADDRESS | 0xffffffff |
| LOADDRESS | 0x0 |
BUSMASTERPORTCONNECTION | DATA |
| CONNECTION | bus1 |
| HIADDRESS | 0xffffffff |
| LOADDRESS | 0x0 |
BUS | bus1 |
| ADDRESSWIDTH | 32 |
MEMORYINSTANCE | ram1 |
VLNVREFERENCE | ram |
BUSSLAVEPORTCONNECTION | sp1 |
| CONNECTION | bus1 |
| HIADDRESS | 0xffffffff |
| LOADDRESS | 0x0 |
FILEVERSION | _version |
| MAJOR | 1 |
| MINOR | 0 |
HW | robustConstitution |
BUS | bus2 |
| ADDRESSWIDTH | 32 |
MEMORYINSTANCE | memory2 |
VLNVREFERENCE | ram |
BUSSLAVEPORTCONNECTION | sp1 |
| CONNECTION | bus2 |
| HIADDRESS | 0xffffffff |
| LOADDRESS | 0x0 |
PROCESSORINSTANCE | appProc2 |
| ID | 1 |
| IMAGEFILE | constitutionIn.exe |
| ENDIAN | little |
VLNVREFERENCE | DC_570T |
BUSMASTERPORTCONNECTION | INSTRUCTION |
| CONNECTION | bus2 |
| HIADDRESS | 0xffffffff |
| LOADDRESS | 0x0 |
BUSMASTERPORTCONNECTION | DATA |
| CONNECTION | bus2 |
| HIADDRESS | 0xffffffff |
| LOADDRESS | 0x0 |
FIFOPORTCONNECTION | IPQ |
| TYPE | input |
| CONNECTION | fifo1 |
BUS | bus1 |
| ADDRESSWIDTH | 32 |
FIFO | fifo1 |
| WIDTH | 32 |
| DEPTH | 7 |
MEMORYINSTANCE | memory1 |
VLNVREFERENCE | ram |
BUSSLAVEPORTCONNECTION | sp1 |
| CONNECTION | bus1 |
| HIADDRESS | 0xffffffff |
| LOADDRESS | 0x0 |
PROCESSORINSTANCE | appProc1 |
| ID | 0 |
| IMAGEFILE | constitutionOut.exe |
| ENDIAN | little |
VLNVREFERENCE | DC_570T |
BUSMASTERPORTCONNECTION | INSTRUCTION |
| CONNECTION | bus1 |
| HIADDRESS | 0xffffffff |
| LOADDRESS | 0x0 |
BUSMASTERPORTCONNECTION | DATA |
| CONNECTION | bus1 |
| HIADDRESS | 0xffffffff |
| LOADDRESS | 0x0 |
FIFOPORTCONNECTION | OPQ |
| TYPE | output |
| CONNECTION | fifo1 |
FILEVERSION | _version |
| MAJOR | 1 |
| MINOR | 0 |
HW | DC_570T_be |
PROCESSORINSTANCE | cpuA |
| ID | 0 |
| TRAP | 1 |
| ENDIAN | big |
VLNVREFERENCE | DC_570T |
BUSMASTERPORTCONNECTION | INSTRUCTION |
| CONNECTION | bus1 |
| HIADDRESS | 0xffffffff |
| LOADDRESS | 0x0 |
BUSMASTERPORTCONNECTION | DATA |
| CONNECTION | bus1 |
| HIADDRESS | 0xffffffff |
| LOADDRESS | 0x0 |
BUS | bus1 |
| ADDRESSWIDTH | 32 |
MEMORYINSTANCE | ram1 |
| ISSEMAPHORE | F |
VLNVREFERENCE | ram |
BUSSLAVEPORTCONNECTION | sp1 |
| CONNECTION | bus1 |
| HIADDRESS | 0xffffffff |
| LOADDRESS | 0x0 |
FILEVERSION | _version |
| MAJOR | 1 |
| MINOR | 0 |
PROCESSOR | DC_B_106micro |
| ENDIAN | either |
| ELFCODE | 94 |
| ATTRIBUTETABLE | modelAttrs |
| LIBRARY | processor |
| LOADPHYSICAL | F |
| IMAGEFILE | model |
| GDBPATH | ${XTENSA_BIN}/xt-gdb |
| GDBFLAGS | --xtensa-core=DC_B_106micro |
| SIGNATURE | 0 |
| VENDOR | ovpworld.org |
| VERSION | 1.0 |
| License | Open Source Apache 2.0 |
| Description | Tensilica (RevB Silicon) DC_B_106micro ISS integration. |
| Limitations | Does not currently support debug. |
BUSMASTERPORT | INSTRUCTION |
| ADDRESSWIDTH | 32 |
| MUSTBECONNECTED | F |
BUSMASTERPORT | DATA |
| ADDRESSWIDTH | 32 |
| MUSTBECONNECTED | F |
REGISTERS | registers |
REGISTER | mr0 |
| WIDTH | 32 |
| TYPE | 4 |
| READONLY | T |
REGISTER | mr1 |
| WIDTH | 32 |
| TYPE | 2 |
| READONLY | F |
REGISTER | mr2 |
| WIDTH | 32 |
| TYPE | 3 |
| READONLY | F |
REGISTER | mr3 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | lbeg |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | lend |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | lcount |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | acclo |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | acchi |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | sar |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | litbaddr |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ps |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | scompare1 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | expstate |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | pc |
| WIDTH | 32 |
| TYPE | 1 |
| READONLY | F |
REGISTER | ar0 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar1 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar2 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar3 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar4 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar5 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar6 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar7 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar8 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar9 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar10 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar11 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar12 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar13 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar14 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar15 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | windowbase |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | windowstart |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
FILEVERSION | _version |
| MAJOR | 1 |
| MINOR | 0 |
PROCESSOR | DC_B_108mini |
| ENDIAN | either |
| ELFCODE | 94 |
| ATTRIBUTETABLE | modelAttrs |
| LIBRARY | processor |
| LOADPHYSICAL | F |
| IMAGEFILE | model |
| GDBPATH | ${XTENSA_BIN}/xt-gdb |
| GDBFLAGS | --xtensa-core=DC_B_108mini |
| SIGNATURE | 0 |
| VENDOR | ovpworld.org |
| VERSION | 1.0 |
| License | Open Source Apache 2.0 |
| Description | Tensilica (RevB Silicon) DC_B_108mini ISS integration. |
| Limitations | Does not currently support debug. |
BUSMASTERPORT | INSTRUCTION |
| ADDRESSWIDTH | 32 |
| MUSTBECONNECTED | F |
BUSMASTERPORT | DATA |
| ADDRESSWIDTH | 32 |
| MUSTBECONNECTED | F |
REGISTERS | registers |
REGISTER | mr0 |
| WIDTH | 32 |
| TYPE | 4 |
| READONLY | T |
REGISTER | mr1 |
| WIDTH | 32 |
| TYPE | 2 |
| READONLY | F |
REGISTER | mr2 |
| WIDTH | 32 |
| TYPE | 3 |
| READONLY | F |
REGISTER | mr3 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | lbeg |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | lend |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | lcount |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | acclo |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | acchi |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | sar |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | litbaddr |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ps |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | scompare1 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | expstate |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | pc |
| WIDTH | 32 |
| TYPE | 1 |
| READONLY | F |
REGISTER | ar0 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar1 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar2 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar3 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar4 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar5 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar6 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar7 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar8 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar9 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar10 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar11 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar12 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar13 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar14 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar15 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | windowbase |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | windowstart |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
FILEVERSION | _version |
| MAJOR | 1 |
| MINOR | 0 |
PROCESSOR | DC_B_212GP |
| ENDIAN | either |
| ELFCODE | 94 |
| ATTRIBUTETABLE | modelAttrs |
| LIBRARY | processor |
| LOADPHYSICAL | F |
| IMAGEFILE | model |
| GDBPATH | ${XTENSA_BIN}/xt-gdb |
| GDBFLAGS | --xtensa-core=DC_B_212GP |
| SIGNATURE | 0 |
| VENDOR | ovpworld.org |
| VERSION | 1.0 |
| License | Open Source Apache 2.0 |
| Description | Tensilica (RevB Silicon) DC_B_212GP ISS integration. |
| Limitations | Does not currently support debug. |
BUSMASTERPORT | INSTRUCTION |
| ADDRESSWIDTH | 32 |
| MUSTBECONNECTED | F |
BUSMASTERPORT | DATA |
| ADDRESSWIDTH | 32 |
| MUSTBECONNECTED | F |
REGISTERS | registers |
REGISTER | mr0 |
| WIDTH | 32 |
| TYPE | 4 |
| READONLY | T |
REGISTER | mr1 |
| WIDTH | 32 |
| TYPE | 2 |
| READONLY | F |
REGISTER | mr2 |
| WIDTH | 32 |
| TYPE | 3 |
| READONLY | F |
REGISTER | mr3 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | lbeg |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | lend |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | lcount |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | acclo |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | acchi |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | sar |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | litbaddr |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ps |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | scompare1 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | expstate |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | pc |
| WIDTH | 32 |
| TYPE | 1 |
| READONLY | F |
REGISTER | ar0 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar1 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar2 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar3 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar4 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar5 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar6 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar7 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar8 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar9 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar10 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar11 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar12 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar13 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar14 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar15 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | windowbase |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | windowstart |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
FILEVERSION | _version |
| MAJOR | 1 |
| MINOR | 0 |
PROCESSOR | DC_B_232L |
| ENDIAN | either |
| ELFCODE | 94 |
| ATTRIBUTETABLE | modelAttrs |
| LIBRARY | processor |
| LOADPHYSICAL | F |
| IMAGEFILE | model |
| GDBPATH | ${XTENSA_BIN}/xt-gdb |
| GDBFLAGS | --xtensa-core=DC_B_232L |
| SIGNATURE | 0 |
| VENDOR | ovpworld.org |
| VERSION | 1.0 |
| License | Open Source Apache 2.0 |
| Description | Tensilica (RevB Silicon) DC_B_232L ISS integration. |
| Limitations | Does not currently support debug. |
BUSMASTERPORT | INSTRUCTION |
| ADDRESSWIDTH | 32 |
| MUSTBECONNECTED | F |
BUSMASTERPORT | DATA |
| ADDRESSWIDTH | 32 |
| MUSTBECONNECTED | F |
REGISTERS | registers |
REGISTER | mr0 |
| WIDTH | 32 |
| TYPE | 4 |
| READONLY | T |
REGISTER | mr1 |
| WIDTH | 32 |
| TYPE | 2 |
| READONLY | F |
REGISTER | mr2 |
| WIDTH | 32 |
| TYPE | 3 |
| READONLY | F |
REGISTER | mr3 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | lbeg |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | lend |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | lcount |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | acclo |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | acchi |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | sar |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | litbaddr |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ps |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | scompare1 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | expstate |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | pc |
| WIDTH | 32 |
| TYPE | 1 |
| READONLY | F |
REGISTER | ar0 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar1 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar2 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar3 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar4 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar5 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar6 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar7 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar8 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar9 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar10 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar11 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar12 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar13 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar14 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar15 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | windowbase |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | windowstart |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
FILEVERSION | _version |
| MAJOR | 1 |
| MINOR | 0 |
PROCESSOR | DC_B_330HiFi |
| ENDIAN | either |
| ELFCODE | 94 |
| ATTRIBUTETABLE | modelAttrs |
| LIBRARY | processor |
| LOADPHYSICAL | F |
| IMAGEFILE | model |
| GDBPATH | ${XTENSA_BIN}/xt-gdb |
| GDBFLAGS | --xtensa-core=DC_B_330HiFi |
| SIGNATURE | 0 |
| VENDOR | ovpworld.org |
| VERSION | 1.0 |
| License | Open Source Apache 2.0 |
| Description | Tensilica (RevB Silicon) DC_B_330HiFi ISS integration. |
| Limitations | Does not currently support debug. |
BUSMASTERPORT | INSTRUCTION |
| ADDRESSWIDTH | 32 |
| MUSTBECONNECTED | F |
BUSMASTERPORT | DATA |
| ADDRESSWIDTH | 32 |
| MUSTBECONNECTED | F |
REGISTERS | registers |
REGISTER | mr0 |
| WIDTH | 32 |
| TYPE | 4 |
| READONLY | T |
REGISTER | mr1 |
| WIDTH | 32 |
| TYPE | 2 |
| READONLY | F |
REGISTER | mr2 |
| WIDTH | 32 |
| TYPE | 3 |
| READONLY | F |
REGISTER | mr3 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | lbeg |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | lend |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | lcount |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | acclo |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | acchi |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | sar |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | litbaddr |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ps |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | scompare1 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | expstate |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | pc |
| WIDTH | 32 |
| TYPE | 1 |
| READONLY | F |
REGISTER | ar0 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar1 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar2 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar3 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar4 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar5 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar6 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar7 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar8 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar9 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar10 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar11 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar12 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar13 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar14 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar15 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | windowbase |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | windowstart |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
FILEVERSION | _version |
| MAJOR | 1 |
| MINOR | 0 |
PROCESSOR | DC_B_545CK |
| ENDIAN | either |
| ELFCODE | 94 |
| ATTRIBUTETABLE | modelAttrs |
| LIBRARY | processor |
| LOADPHYSICAL | F |
| IMAGEFILE | model |
| GDBPATH | ${XTENSA_BIN}/xt-gdb |
| GDBFLAGS | --xtensa-core=DC_B_545CK |
| SIGNATURE | 0 |
| VENDOR | ovpworld.org |
| VERSION | 1.0 |
| License | Open Source Apache 2.0 |
| Description | Tensilica (RevB Silicon) DC_B_545CK ISS integration. |
| Limitations | Does not currently support debug. |
FIFOPORT | IPQ |
| MUSTBECONNECTED | F |
| TYPE | input |
FIFOPORT | OPQ |
| MUSTBECONNECTED | F |
| TYPE | output |
BUSMASTERPORT | INSTRUCTION |
| ADDRESSWIDTH | 32 |
| MUSTBECONNECTED | F |
BUSMASTERPORT | DATA |
| ADDRESSWIDTH | 32 |
| MUSTBECONNECTED | F |
REGISTERS | registers |
REGISTER | mr0 |
| WIDTH | 32 |
| TYPE | 4 |
| READONLY | T |
REGISTER | mr1 |
| WIDTH | 32 |
| TYPE | 2 |
| READONLY | F |
REGISTER | mr2 |
| WIDTH | 32 |
| TYPE | 3 |
| READONLY | F |
REGISTER | mr3 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | lbeg |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | lend |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | lcount |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | acclo |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | acchi |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | sar |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | litbaddr |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ps |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | scompare1 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | expstate |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | pc |
| WIDTH | 32 |
| TYPE | 1 |
| READONLY | F |
REGISTER | ar0 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar1 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar2 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar3 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar4 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar5 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar6 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar7 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar8 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar9 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar10 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar11 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar12 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar13 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar14 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar15 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | windowbase |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | windowstart |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
FILEVERSION | _version |
| MAJOR | 1 |
| MINOR | 0 |
PROCESSOR | DC_B_570T |
| ENDIAN | either |
| ELFCODE | 94 |
| ATTRIBUTETABLE | modelAttrs |
| LIBRARY | processor |
| LOADPHYSICAL | F |
| IMAGEFILE | model |
| GDBPATH | ${XTENSA_BIN}/xt-gdb |
| GDBFLAGS | --xtensa-core=DC_B_108mini |
| SIGNATURE | 0 |
| VENDOR | ovpworld.org |
| VERSION | 1.0 |
| License | Open Source Apache 2.0 |
| Description | Tensilica (RevB Silicon) DC_B_570T ISS integration. |
| Limitations | Does not currently support debug. |
FIFOPORT | IPQ |
| MUSTBECONNECTED | F |
| TYPE | input |
FIFOPORT | OPQ |
| MUSTBECONNECTED | F |
| TYPE | output |
BUSMASTERPORT | INSTRUCTION |
| ADDRESSWIDTH | 32 |
| MUSTBECONNECTED | F |
BUSMASTERPORT | DATA |
| ADDRESSWIDTH | 32 |
| MUSTBECONNECTED | F |
REGISTERS | registers |
REGISTER | mr0 |
| WIDTH | 32 |
| TYPE | 4 |
| READONLY | T |
REGISTER | mr1 |
| WIDTH | 32 |
| TYPE | 2 |
| READONLY | F |
REGISTER | mr2 |
| WIDTH | 32 |
| TYPE | 3 |
| READONLY | F |
REGISTER | mr3 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | lbeg |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | lend |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | lcount |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | acclo |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | acchi |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | sar |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | litbaddr |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ps |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | scompare1 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | expstate |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | pc |
| WIDTH | 32 |
| TYPE | 1 |
| READONLY | F |
REGISTER | ar0 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar1 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar2 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar3 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar4 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar5 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar6 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar7 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar8 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar9 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar10 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar11 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar12 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar13 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar14 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar15 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | windowbase |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | windowstart |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
FILEVERSION | _version |
| MAJOR | 1 |
| MINOR | 0 |
HW | robustConstitution |
BUS | bus2 |
| ADDRESSWIDTH | 32 |
MEMORYINSTANCE | memory2 |
VLNVREFERENCE | ram |
BUSSLAVEPORTCONNECTION | sp1 |
| CONNECTION | bus2 |
| HIADDRESS | 0xffffffff |
| LOADDRESS | 0x0 |
PROCESSORINSTANCE | appProc2 |
| ID | 1 |
| IMAGEFILE | constitutionIn.exe |
| TRAP | 0 |
| ENDIAN | little |
VLNVREFERENCE | DC_B_570T |
BUSMASTERPORTCONNECTION | INSTRUCTION |
| CONNECTION | bus2 |
| HIADDRESS | 0xffffffff |
| LOADDRESS | 0x0 |
BUSMASTERPORTCONNECTION | DATA |
| CONNECTION | bus2 |
| HIADDRESS | 0xffffffff |
| LOADDRESS | 0x0 |
FIFOPORTCONNECTION | IPQ |
| CONNECTION | fifo1 |
BUS | bus1 |
| ADDRESSWIDTH | 32 |
FIFO | fifo1 |
| WIDTH | 32 |
| DEPTH | 7 |
MEMORYINSTANCE | memory1 |
VLNVREFERENCE | ram |
BUSSLAVEPORTCONNECTION | sp1 |
| CONNECTION | bus1 |
| HIADDRESS | 0xffffffff |
| LOADDRESS | 0x0 |
PROCESSORINSTANCE | appProc1 |
| ID | 0 |
| IMAGEFILE | constitutionOut.exe |
| SIMULATEEXCEPTIONS | F |
| TRAP | 0 |
| ENDIAN | little |
VLNVREFERENCE | DC_B_570T |
BUSMASTERPORTCONNECTION | INSTRUCTION |
| CONNECTION | bus1 |
| HIADDRESS | 0xffffffff |
| LOADDRESS | 0x0 |
BUSMASTERPORTCONNECTION | DATA |
| CONNECTION | bus1 |
| HIADDRESS | 0xffffffff |
| LOADDRESS | 0x0 |
FIFOPORTCONNECTION | OPQ |
| CONNECTION | fifo1 |
FILEVERSION | _version |
| MAJOR | 1 |
| MINOR | 0 |
PROCESSOR | TensilicaDiamondCore |
| ENDIAN | either |
| ELFCODE | 94 |
| ATTRIBUTETABLE | modelAttrs |
| LIBRARY | processor |
| LOADPHYSICAL | F |
| IMAGEFILE | model |
| GDBPATH | ${XTENSA_BIN}/xt-gdb |
| GDBFLAGS | --xtensa-core=${XTENSA_CORE} |
| SIGNATURE | 0 |
| VENDOR | ovpworld.org |
| VERSION | 1.0 |
| License | Open Source Apache 2.0 |
| Description | Tensilica DiamondCore ISS integration. Supports cores Version A silicon DC_108mini, DC_212GP, DC_232L, DC_330HiFi, DC_545CK, DC_570T. Version B silicon DC_B_106micro, DC_B_108mini, DC_B_212GP, DC_B_232L, DC_B_330HiFi, DC_B_545CK, DC_B_570T |
PROCESSOR | tensilica |
| ENDIAN | either |
| ELFCODE | 94 |
| ATTRIBUTETABLE | modelAttrs |
| LIBRARY | processor |
| LOADPHYSICAL | F |
| IMAGEFILE | model |
| SIGNATURE | 0 |
| VENDOR | ovpworld.org |
| VERSION | 1.0 |
| License | Open Source Apache 2.0 |
| Description | Tensilica DiamondCores ISS integration. Supports Version A silicon cores DC_108mini, DC_212GP, DC_232L, DC_330HiFi, DC_545CK, DC_570T and Version B silicon cores DC_B_106micro, DC_B_108mini, DC_B_212GP, DC_B_232L, DC_B_330HiFi, DC_B_545CK, DC_B_570T. |
| Limitations | Does not currently support debug. |
BUSMASTERPORT | INSTRUCTION |
| ADDRESSWIDTH | 32 |
| MUSTBECONNECTED | F |
BUSMASTERPORT | DATA |
| ADDRESSWIDTH | 32 |
| MUSTBECONNECTED | F |
REGISTERS | registers |
REGISTER | mr0 |
| WIDTH | 32 |
| TYPE | 4 |
| READONLY | T |
REGISTER | mr1 |
| WIDTH | 32 |
| TYPE | 2 |
| READONLY | F |
REGISTER | mr2 |
| WIDTH | 32 |
| TYPE | 3 |
| READONLY | F |
REGISTER | mr3 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | lbeg |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | lend |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | lcount |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | acclo |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | acchi |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | sar |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | litbaddr |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ps |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | scompare1 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | expstate |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | pc |
| WIDTH | 32 |
| TYPE | 1 |
| READONLY | F |
REGISTER | ar0 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar1 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar2 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar3 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar4 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar5 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar6 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar7 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar8 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar9 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar10 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar11 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar12 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar13 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar14 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | ar15 |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | windowbase |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
REGISTER | windowstart |
| WIDTH | 32 |
| TYPE | 0 |
| READONLY | F |
FILEVERSION | _version |
| MAJOR | 1 |
| MINOR | 0 |
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