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TensilicaDiamond

You can use Tensilica processor models within OVP simulations. This is accomplished by 'wrapping' the Tensilica processor model with an 'integration adaptor' to encapsulate it and make it appear to an OVP platform as a normal OVP processor model.

Click to log in before viewing / downloadingDOWNLOAD OVP Tensilica ISS Integration Adapter
TensilicaDiamond.zip / 28.63 KB


Tensilica Diamond Core ISS Encapsulation Example
There is an encapsulation of Tensilica Diamond Core processors available for use in OVP. Usage of this integration is shown in the normal OVPsim installer download by an example platform:
Examples/Vendors/Tensilica/DC_570Tx2
Some general details about this example platform and specific details of the encapsulation are given here.

Prerequisites
In order to use the encapsulation, you must have available and installed the Tensilica Turbo Xim fast functional simulator. In order to create applications, you will also need to install the Tensilica compiler toolchain. Visit www.tensilica.com for more information.

Example details
See the file README.txt in the example directory for a description of the encapsulation example.

Encapsulation Details
The Tensilica Turbo Xim fast functional simulator is encapsulated by an OVP wrapper. The encapsulation can support any processor type supported by the Tensilica simulator - the specific variant is defined by the processor type string when a processor instance is created. The example platform contains two instances of the DC_570T core (the variant is set in the Makefile). Consult the Tensilica documentation for a full list of processor variants supported by Turbo Xim.
OVP FIFO objects can be used to connect Tensilica processors if required. In the example platform, a single 8-entry FIFO is used to connect the two DC_570T cores, and a text message is passed between the cores using the FIFO.

Restrictions (June 08)
The encapsulation doesn't currently support the Imperas Multi-Core Debugger. In the current release the encapsulated Tensilica processor can be debugged with GDB. This restriction will hopefully be addressed with the next release of the Tensilica Turbo Xim simulator.

For more information about this encapsulation - please contact us at info[at]ovpworld.org or via the www.ovpworld.org/forum.


  Attachment Size Date Added
      DC_108mini.xml   1.05 KB   11/22/2016 5:52 pm
      DC_108mini_2.xml   1.84 KB   11/22/2016 5:52 pm
      DC_108mini_be.xml   1.07 KB   11/22/2016 5:52 pm
      DC_212GP.xml   4.32 KB   11/22/2016 5:52 pm
      DC_232L.xml   4.32 KB   11/22/2016 5:52 pm
      DC_330HiFi.xml   4.33 KB   11/22/2016 5:52 pm
      DC_545CK.xml   4.32 KB   11/22/2016 5:52 pm
      DC_570T.xml   1.07 KB   11/22/2016 5:52 pm
      DC_570T_2.xml   2.25 KB   11/22/2016 5:52 pm
      DC_570T_be.xml   1.09 KB   11/22/2016 5:52 pm
      DC_B_106micro.xml   4.35 KB   11/22/2016 5:52 pm
      DC_B_108mini.xml   4.35 KB   11/22/2016 5:52 pm
      DC_B_212GP.xml   4.34 KB   11/22/2016 5:52 pm
      DC_B_232L.xml   4.34 KB   11/22/2016 5:52 pm
      DC_B_330HiFi.xml   4.35 KB   11/22/2016 5:52 pm
      DC_B_545CK.xml   4.5 KB   11/22/2016 5:52 pm
      DC_B_570T.xml   4.5 KB   11/22/2016 5:52 pm
      DC_B_570T_2.xml   2.26 KB   11/22/2016 5:52 pm
      diamondCore.model.xml   4.48 KB   11/22/2016 5:52 pm
      tensilica.model.xml   4.47 KB   11/22/2016 5:52 pm
      TensilicaDiamond.zip   28.63 KB   11/22/2016 5:52 pm
 

Component Description for TensilicaDiamond/DC_108mini.xml

HW

DC_108mini

PROCESSORINSTANCE

cpuA

ID0
TRAP1
VLNVREFERENCE
DC_108mini
BUSMASTERPORTCONNECTION
INSTRUCTION
CONNECTIONbus1
HIADDRESS0xffffffff
LOADDRESS0x0
BUSMASTERPORTCONNECTION
DATA
CONNECTIONbus1
HIADDRESS0xffffffff
LOADDRESS0x0

BUS

bus1

ADDRESSWIDTH32

MEMORYINSTANCE

ram1

VLNVREFERENCE
ram
BUSSLAVEPORTCONNECTION
sp1
CONNECTIONbus1
HIADDRESS0xffffffff
LOADDRESS0x0

FILEVERSION

_version

MAJOR1
MINOR0


Component Description for TensilicaDiamond/DC_108mini_2.xml

HW

DC_108mini2

PROCESSORINSTANCE

cpuA

ID0
TRAP1
VLNVREFERENCE
DC_108mini
BUSMASTERPORTCONNECTION
INSTRUCTION
CONNECTIONbus1
HIADDRESS0xffffffff
LOADDRESS0x0
BUSMASTERPORTCONNECTION
DATA
CONNECTIONbus1
HIADDRESS0xffffffff
LOADDRESS0x0

BUS

bus1

ADDRESSWIDTH32

MEMORYINSTANCE

ram1

VLNVREFERENCE
ram
BUSSLAVEPORTCONNECTION
sp1
CONNECTIONbus1
HIADDRESS0xffffffff
LOADDRESS0x0

PROCESSORINSTANCE

cpuB

ID1
TRAP1
VLNVREFERENCE
DC_108mini
BUSMASTERPORTCONNECTION
INSTRUCTION
CONNECTIONbus2
HIADDRESS0xffffffff
LOADDRESS0x0
BUSMASTERPORTCONNECTION
DATA
CONNECTIONbus2
HIADDRESS0xffffffff
LOADDRESS0x0

BUS

bus2

ADDRESSWIDTH32

MEMORYINSTANCE

ram2

VLNVREFERENCE
ram
BUSSLAVEPORTCONNECTION
sp1
CONNECTIONbus2
HIADDRESS0xffffffff
LOADDRESS0x0

FILEVERSION

_version

MAJOR1
MINOR0


Component Description for TensilicaDiamond/DC_108mini_be.xml

HW

DC_108mini_be

PROCESSORINSTANCE

cpuA

ID0
TRAP1
ENDIANbig
VLNVREFERENCE
DC_108mini
BUSMASTERPORTCONNECTION
INSTRUCTION
CONNECTIONbus1
HIADDRESS0xffffffff
LOADDRESS0x0
BUSMASTERPORTCONNECTION
DATA
CONNECTIONbus1
HIADDRESS0xffffffff
LOADDRESS0x0

BUS

bus1

ADDRESSWIDTH32

MEMORYINSTANCE

ram1

VLNVREFERENCE
ram
BUSSLAVEPORTCONNECTION
sp1
CONNECTIONbus1
HIADDRESS0xffffffff
LOADDRESS0x0

FILEVERSION

_version

MAJOR1
MINOR0


Component Description for TensilicaDiamond/DC_212GP.xml

PROCESSOR

DC_212GP

ENDIANeither
ELFCODE94
ATTRIBUTETABLEmodelAttrs
LIBRARYprocessor
LOADPHYSICALF
IMAGEFILEmodel
GDBPATH${XTENSA_BIN}/xt-gdb
GDBFLAGS--xtensa-core=DC_212GP
SIGNATURE0
VENDORovpworld.org
VERSION1.0
LicenseOpen Source Apache 2.0
DescriptionTensilica DC_212GP ISS integration.
LimitationsDoes not currently support debug.

BUSMASTERPORT

INSTRUCTION

ADDRESSWIDTH32
MUSTBECONNECTEDF

BUSMASTERPORT

DATA

ADDRESSWIDTH32
MUSTBECONNECTEDF

REGISTERS

registers

REGISTER
mr0
WIDTH32
TYPE4
READONLYT
REGISTER
mr1
WIDTH32
TYPE2
READONLYF
REGISTER
mr2
WIDTH32
TYPE3
READONLYF
REGISTER
mr3
WIDTH32
TYPE0
READONLYF
REGISTER
lbeg
WIDTH32
TYPE0
READONLYF
REGISTER
lend
WIDTH32
TYPE0
READONLYF
REGISTER
lcount
WIDTH32
TYPE0
READONLYF
REGISTER
acclo
WIDTH32
TYPE0
READONLYF
REGISTER
acchi
WIDTH32
TYPE0
READONLYF
REGISTER
sar
WIDTH32
TYPE0
READONLYF
REGISTER
litbaddr
WIDTH32
TYPE0
READONLYF
REGISTER
ps
WIDTH32
TYPE0
READONLYF
REGISTER
scompare1
WIDTH32
TYPE0
READONLYF
REGISTER
expstate
WIDTH32
TYPE0
READONLYF
REGISTER
pc
WIDTH32
TYPE1
READONLYF
REGISTER
ar0
WIDTH32
TYPE0
READONLYF
REGISTER
ar1
WIDTH32
TYPE0
READONLYF
REGISTER
ar2
WIDTH32
TYPE0
READONLYF
REGISTER
ar3
WIDTH32
TYPE0
READONLYF
REGISTER
ar4
WIDTH32
TYPE0
READONLYF
REGISTER
ar5
WIDTH32
TYPE0
READONLYF
REGISTER
ar6
WIDTH32
TYPE0
READONLYF
REGISTER
ar7
WIDTH32
TYPE0
READONLYF
REGISTER
ar8
WIDTH32
TYPE0
READONLYF
REGISTER
ar9
WIDTH32
TYPE0
READONLYF
REGISTER
ar10
WIDTH32
TYPE0
READONLYF
REGISTER
ar11
WIDTH32
TYPE0
READONLYF
REGISTER
ar12
WIDTH32
TYPE0
READONLYF
REGISTER
ar13
WIDTH32
TYPE0
READONLYF
REGISTER
ar14
WIDTH32
TYPE0
READONLYF
REGISTER
ar15
WIDTH32
TYPE0
READONLYF
REGISTER
windowbase
WIDTH32
TYPE0
READONLYF
REGISTER
windowstart
WIDTH32
TYPE0
READONLYF

FILEVERSION

_version

MAJOR1
MINOR0


Component Description for TensilicaDiamond/DC_232L.xml

PROCESSOR

DC_232L

ENDIANeither
ELFCODE94
ATTRIBUTETABLEmodelAttrs
LIBRARYprocessor
LOADPHYSICALF
IMAGEFILEmodel
GDBPATH${XTENSA_BIN}/xt-gdb
GDBFLAGS--xtensa-core=DC_232L
SIGNATURE0
VENDORovpworld.org
VERSION1.0
LicenseOpen Source Apache 2.0
DescriptionTensilica DC_232L ISS integration.
LimitationsDoes not currently support debug.

BUSMASTERPORT

INSTRUCTION

ADDRESSWIDTH32
MUSTBECONNECTEDF

BUSMASTERPORT

DATA

ADDRESSWIDTH32
MUSTBECONNECTEDF

REGISTERS

registers

REGISTER
mr0
WIDTH32
TYPE4
READONLYT
REGISTER
mr1
WIDTH32
TYPE2
READONLYF
REGISTER
mr2
WIDTH32
TYPE3
READONLYF
REGISTER
mr3
WIDTH32
TYPE0
READONLYF
REGISTER
lbeg
WIDTH32
TYPE0
READONLYF
REGISTER
lend
WIDTH32
TYPE0
READONLYF
REGISTER
lcount
WIDTH32
TYPE0
READONLYF
REGISTER
acclo
WIDTH32
TYPE0
READONLYF
REGISTER
acchi
WIDTH32
TYPE0
READONLYF
REGISTER
sar
WIDTH32
TYPE0
READONLYF
REGISTER
litbaddr
WIDTH32
TYPE0
READONLYF
REGISTER
ps
WIDTH32
TYPE0
READONLYF
REGISTER
scompare1
WIDTH32
TYPE0
READONLYF
REGISTER
expstate
WIDTH32
TYPE0
READONLYF
REGISTER
pc
WIDTH32
TYPE1
READONLYF
REGISTER
ar0
WIDTH32
TYPE0
READONLYF
REGISTER
ar1
WIDTH32
TYPE0
READONLYF
REGISTER
ar2
WIDTH32
TYPE0
READONLYF
REGISTER
ar3
WIDTH32
TYPE0
READONLYF
REGISTER
ar4
WIDTH32
TYPE0
READONLYF
REGISTER
ar5
WIDTH32
TYPE0
READONLYF
REGISTER
ar6
WIDTH32
TYPE0
READONLYF
REGISTER
ar7
WIDTH32
TYPE0
READONLYF
REGISTER
ar8
WIDTH32
TYPE0
READONLYF
REGISTER
ar9
WIDTH32
TYPE0
READONLYF
REGISTER
ar10
WIDTH32
TYPE0
READONLYF
REGISTER
ar11
WIDTH32
TYPE0
READONLYF
REGISTER
ar12
WIDTH32
TYPE0
READONLYF
REGISTER
ar13
WIDTH32
TYPE0
READONLYF
REGISTER
ar14
WIDTH32
TYPE0
READONLYF
REGISTER
ar15
WIDTH32
TYPE0
READONLYF
REGISTER
windowbase
WIDTH32
TYPE0
READONLYF
REGISTER
windowstart
WIDTH32
TYPE0
READONLYF

FILEVERSION

_version

MAJOR1
MINOR0


Component Description for TensilicaDiamond/DC_330HiFi.xml

PROCESSOR

DC_330HiFi

ENDIANeither
ELFCODE94
ATTRIBUTETABLEmodelAttrs
LIBRARYprocessor
LOADPHYSICALF
IMAGEFILEmodel
GDBPATH${XTENSA_BIN}/xt-gdb
GDBFLAGS--xtensa-core=DC_330HiFi
SIGNATURE0
VENDORovpworld.org
VERSION1.0
LicenseOpen Source Apache 2.0
DescriptionTensilica DC_330HiFi ISS integration.
LimitationsDoes not currently support debug.

BUSMASTERPORT

INSTRUCTION

ADDRESSWIDTH32
MUSTBECONNECTEDF

BUSMASTERPORT

DATA

ADDRESSWIDTH32
MUSTBECONNECTEDF

REGISTERS

registers

REGISTER
mr0
WIDTH32
TYPE4
READONLYT
REGISTER
mr1
WIDTH32
TYPE2
READONLYF
REGISTER
mr2
WIDTH32
TYPE3
READONLYF
REGISTER
mr3
WIDTH32
TYPE0
READONLYF
REGISTER
lbeg
WIDTH32
TYPE0
READONLYF
REGISTER
lend
WIDTH32
TYPE0
READONLYF
REGISTER
lcount
WIDTH32
TYPE0
READONLYF
REGISTER
acclo
WIDTH32
TYPE0
READONLYF
REGISTER
acchi
WIDTH32
TYPE0
READONLYF
REGISTER
sar
WIDTH32
TYPE0
READONLYF
REGISTER
litbaddr
WIDTH32
TYPE0
READONLYF
REGISTER
ps
WIDTH32
TYPE0
READONLYF
REGISTER
scompare1
WIDTH32
TYPE0
READONLYF
REGISTER
expstate
WIDTH32
TYPE0
READONLYF
REGISTER
pc
WIDTH32
TYPE1
READONLYF
REGISTER
ar0
WIDTH32
TYPE0
READONLYF
REGISTER
ar1
WIDTH32
TYPE0
READONLYF
REGISTER
ar2
WIDTH32
TYPE0
READONLYF
REGISTER
ar3
WIDTH32
TYPE0
READONLYF
REGISTER
ar4
WIDTH32
TYPE0
READONLYF
REGISTER
ar5
WIDTH32
TYPE0
READONLYF
REGISTER
ar6
WIDTH32
TYPE0
READONLYF
REGISTER
ar7
WIDTH32
TYPE0
READONLYF
REGISTER
ar8
WIDTH32
TYPE0
READONLYF
REGISTER
ar9
WIDTH32
TYPE0
READONLYF
REGISTER
ar10
WIDTH32
TYPE0
READONLYF
REGISTER
ar11
WIDTH32
TYPE0
READONLYF
REGISTER
ar12
WIDTH32
TYPE0
READONLYF
REGISTER
ar13
WIDTH32
TYPE0
READONLYF
REGISTER
ar14
WIDTH32
TYPE0
READONLYF
REGISTER
ar15
WIDTH32
TYPE0
READONLYF
REGISTER
windowbase
WIDTH32
TYPE0
READONLYF
REGISTER
windowstart
WIDTH32
TYPE0
READONLYF

FILEVERSION

_version

MAJOR1
MINOR0


Component Description for TensilicaDiamond/DC_545CK.xml

PROCESSOR

DC_545CK

ENDIANeither
ELFCODE94
ATTRIBUTETABLEmodelAttrs
LIBRARYprocessor
LOADPHYSICALF
IMAGEFILEmodel
GDBPATH${XTENSA_BIN}/xt-gdb
GDBFLAGS--xtensa-core=DC_545CK
SIGNATURE0
VENDORovpworld.org
VERSION1.0
LicenseOpen Source Apache 2.0
DescriptionTensilica DC_545CK ISS integration.
LimitationsDoes not currently support debug.

BUSMASTERPORT

INSTRUCTION

ADDRESSWIDTH32
MUSTBECONNECTEDF

BUSMASTERPORT

DATA

ADDRESSWIDTH32
MUSTBECONNECTEDF

REGISTERS

registers

REGISTER
mr0
WIDTH32
TYPE4
READONLYT
REGISTER
mr1
WIDTH32
TYPE2
READONLYF
REGISTER
mr2
WIDTH32
TYPE3
READONLYF
REGISTER
mr3
WIDTH32
TYPE0
READONLYF
REGISTER
lbeg
WIDTH32
TYPE0
READONLYF
REGISTER
lend
WIDTH32
TYPE0
READONLYF
REGISTER
lcount
WIDTH32
TYPE0
READONLYF
REGISTER
acclo
WIDTH32
TYPE0
READONLYF
REGISTER
acchi
WIDTH32
TYPE0
READONLYF
REGISTER
sar
WIDTH32
TYPE0
READONLYF
REGISTER
litbaddr
WIDTH32
TYPE0
READONLYF
REGISTER
ps
WIDTH32
TYPE0
READONLYF
REGISTER
scompare1
WIDTH32
TYPE0
READONLYF
REGISTER
expstate
WIDTH32
TYPE0
READONLYF
REGISTER
pc
WIDTH32
TYPE1
READONLYF
REGISTER
ar0
WIDTH32
TYPE0
READONLYF
REGISTER
ar1
WIDTH32
TYPE0
READONLYF
REGISTER
ar2
WIDTH32
TYPE0
READONLYF
REGISTER
ar3
WIDTH32
TYPE0
READONLYF
REGISTER
ar4
WIDTH32
TYPE0
READONLYF
REGISTER
ar5
WIDTH32
TYPE0
READONLYF
REGISTER
ar6
WIDTH32
TYPE0
READONLYF
REGISTER
ar7
WIDTH32
TYPE0
READONLYF
REGISTER
ar8
WIDTH32
TYPE0
READONLYF
REGISTER
ar9
WIDTH32
TYPE0
READONLYF
REGISTER
ar10
WIDTH32
TYPE0
READONLYF
REGISTER
ar11
WIDTH32
TYPE0
READONLYF
REGISTER
ar12
WIDTH32
TYPE0
READONLYF
REGISTER
ar13
WIDTH32
TYPE0
READONLYF
REGISTER
ar14
WIDTH32
TYPE0
READONLYF
REGISTER
ar15
WIDTH32
TYPE0
READONLYF
REGISTER
windowbase
WIDTH32
TYPE0
READONLYF
REGISTER
windowstart
WIDTH32
TYPE0
READONLYF

FILEVERSION

_version

MAJOR1
MINOR0


Component Description for TensilicaDiamond/DC_570T.xml

HW

DC_570T

PROCESSORINSTANCE

cpuA

ID0
TRAP1
ENDIANlittle
VLNVREFERENCE
DC_570T
BUSMASTERPORTCONNECTION
INSTRUCTION
CONNECTIONbus1
HIADDRESS0xffffffff
LOADDRESS0x0
BUSMASTERPORTCONNECTION
DATA
CONNECTIONbus1
HIADDRESS0xffffffff
LOADDRESS0x0

BUS

bus1

ADDRESSWIDTH32

MEMORYINSTANCE

ram1

VLNVREFERENCE
ram
BUSSLAVEPORTCONNECTION
sp1
CONNECTIONbus1
HIADDRESS0xffffffff
LOADDRESS0x0

FILEVERSION

_version

MAJOR1
MINOR0


Component Description for TensilicaDiamond/DC_570T_2.xml

HW

robustConstitution

BUS

bus2

ADDRESSWIDTH32

MEMORYINSTANCE

memory2

VLNVREFERENCE
ram
BUSSLAVEPORTCONNECTION
sp1
CONNECTIONbus2
HIADDRESS0xffffffff
LOADDRESS0x0

PROCESSORINSTANCE

appProc2

ID1
IMAGEFILEconstitutionIn.exe
ENDIANlittle
VLNVREFERENCE
DC_570T
BUSMASTERPORTCONNECTION
INSTRUCTION
CONNECTIONbus2
HIADDRESS0xffffffff
LOADDRESS0x0
BUSMASTERPORTCONNECTION
DATA
CONNECTIONbus2
HIADDRESS0xffffffff
LOADDRESS0x0
FIFOPORTCONNECTION
IPQ
TYPEinput
CONNECTIONfifo1

BUS

bus1

ADDRESSWIDTH32

FIFO

fifo1

WIDTH32
DEPTH7

MEMORYINSTANCE

memory1

VLNVREFERENCE
ram
BUSSLAVEPORTCONNECTION
sp1
CONNECTIONbus1
HIADDRESS0xffffffff
LOADDRESS0x0

PROCESSORINSTANCE

appProc1

ID0
IMAGEFILEconstitutionOut.exe
ENDIANlittle
VLNVREFERENCE
DC_570T
BUSMASTERPORTCONNECTION
INSTRUCTION
CONNECTIONbus1
HIADDRESS0xffffffff
LOADDRESS0x0
BUSMASTERPORTCONNECTION
DATA
CONNECTIONbus1
HIADDRESS0xffffffff
LOADDRESS0x0
FIFOPORTCONNECTION
OPQ
TYPEoutput
CONNECTIONfifo1

FILEVERSION

_version

MAJOR1
MINOR0


Component Description for TensilicaDiamond/DC_570T_be.xml

HW

DC_570T_be

PROCESSORINSTANCE

cpuA

ID0
TRAP1
ENDIANbig
VLNVREFERENCE
DC_570T
BUSMASTERPORTCONNECTION
INSTRUCTION
CONNECTIONbus1
HIADDRESS0xffffffff
LOADDRESS0x0
BUSMASTERPORTCONNECTION
DATA
CONNECTIONbus1
HIADDRESS0xffffffff
LOADDRESS0x0

BUS

bus1

ADDRESSWIDTH32

MEMORYINSTANCE

ram1

ISSEMAPHOREF
VLNVREFERENCE
ram
BUSSLAVEPORTCONNECTION
sp1
CONNECTIONbus1
HIADDRESS0xffffffff
LOADDRESS0x0

FILEVERSION

_version

MAJOR1
MINOR0


Component Description for TensilicaDiamond/DC_B_106micro.xml

PROCESSOR

DC_B_106micro

ENDIANeither
ELFCODE94
ATTRIBUTETABLEmodelAttrs
LIBRARYprocessor
LOADPHYSICALF
IMAGEFILEmodel
GDBPATH${XTENSA_BIN}/xt-gdb
GDBFLAGS--xtensa-core=DC_B_106micro
SIGNATURE0
VENDORovpworld.org
VERSION1.0
LicenseOpen Source Apache 2.0
DescriptionTensilica (RevB Silicon) DC_B_106micro ISS integration.
LimitationsDoes not currently support debug.

BUSMASTERPORT

INSTRUCTION

ADDRESSWIDTH32
MUSTBECONNECTEDF

BUSMASTERPORT

DATA

ADDRESSWIDTH32
MUSTBECONNECTEDF

REGISTERS

registers

REGISTER
mr0
WIDTH32
TYPE4
READONLYT
REGISTER
mr1
WIDTH32
TYPE2
READONLYF
REGISTER
mr2
WIDTH32
TYPE3
READONLYF
REGISTER
mr3
WIDTH32
TYPE0
READONLYF
REGISTER
lbeg
WIDTH32
TYPE0
READONLYF
REGISTER
lend
WIDTH32
TYPE0
READONLYF
REGISTER
lcount
WIDTH32
TYPE0
READONLYF
REGISTER
acclo
WIDTH32
TYPE0
READONLYF
REGISTER
acchi
WIDTH32
TYPE0
READONLYF
REGISTER
sar
WIDTH32
TYPE0
READONLYF
REGISTER
litbaddr
WIDTH32
TYPE0
READONLYF
REGISTER
ps
WIDTH32
TYPE0
READONLYF
REGISTER
scompare1
WIDTH32
TYPE0
READONLYF
REGISTER
expstate
WIDTH32
TYPE0
READONLYF
REGISTER
pc
WIDTH32
TYPE1
READONLYF
REGISTER
ar0
WIDTH32
TYPE0
READONLYF
REGISTER
ar1
WIDTH32
TYPE0
READONLYF
REGISTER
ar2
WIDTH32
TYPE0
READONLYF
REGISTER
ar3
WIDTH32
TYPE0
READONLYF
REGISTER
ar4
WIDTH32
TYPE0
READONLYF
REGISTER
ar5
WIDTH32
TYPE0
READONLYF
REGISTER
ar6
WIDTH32
TYPE0
READONLYF
REGISTER
ar7
WIDTH32
TYPE0
READONLYF
REGISTER
ar8
WIDTH32
TYPE0
READONLYF
REGISTER
ar9
WIDTH32
TYPE0
READONLYF
REGISTER
ar10
WIDTH32
TYPE0
READONLYF
REGISTER
ar11
WIDTH32
TYPE0
READONLYF
REGISTER
ar12
WIDTH32
TYPE0
READONLYF
REGISTER
ar13
WIDTH32
TYPE0
READONLYF
REGISTER
ar14
WIDTH32
TYPE0
READONLYF
REGISTER
ar15
WIDTH32
TYPE0
READONLYF
REGISTER
windowbase
WIDTH32
TYPE0
READONLYF
REGISTER
windowstart
WIDTH32
TYPE0
READONLYF

FILEVERSION

_version

MAJOR1
MINOR0


Component Description for TensilicaDiamond/DC_B_108mini.xml

PROCESSOR

DC_B_108mini

ENDIANeither
ELFCODE94
ATTRIBUTETABLEmodelAttrs
LIBRARYprocessor
LOADPHYSICALF
IMAGEFILEmodel
GDBPATH${XTENSA_BIN}/xt-gdb
GDBFLAGS--xtensa-core=DC_B_108mini
SIGNATURE0
VENDORovpworld.org
VERSION1.0
LicenseOpen Source Apache 2.0
DescriptionTensilica (RevB Silicon) DC_B_108mini ISS integration.
LimitationsDoes not currently support debug.

BUSMASTERPORT

INSTRUCTION

ADDRESSWIDTH32
MUSTBECONNECTEDF

BUSMASTERPORT

DATA

ADDRESSWIDTH32
MUSTBECONNECTEDF

REGISTERS

registers

REGISTER
mr0
WIDTH32
TYPE4
READONLYT
REGISTER
mr1
WIDTH32
TYPE2
READONLYF
REGISTER
mr2
WIDTH32
TYPE3
READONLYF
REGISTER
mr3
WIDTH32
TYPE0
READONLYF
REGISTER
lbeg
WIDTH32
TYPE0
READONLYF
REGISTER
lend
WIDTH32
TYPE0
READONLYF
REGISTER
lcount
WIDTH32
TYPE0
READONLYF
REGISTER
acclo
WIDTH32
TYPE0
READONLYF
REGISTER
acchi
WIDTH32
TYPE0
READONLYF
REGISTER
sar
WIDTH32
TYPE0
READONLYF
REGISTER
litbaddr
WIDTH32
TYPE0
READONLYF
REGISTER
ps
WIDTH32
TYPE0
READONLYF
REGISTER
scompare1
WIDTH32
TYPE0
READONLYF
REGISTER
expstate
WIDTH32
TYPE0
READONLYF
REGISTER
pc
WIDTH32
TYPE1
READONLYF
REGISTER
ar0
WIDTH32
TYPE0
READONLYF
REGISTER
ar1
WIDTH32
TYPE0
READONLYF
REGISTER
ar2
WIDTH32
TYPE0
READONLYF
REGISTER
ar3
WIDTH32
TYPE0
READONLYF
REGISTER
ar4
WIDTH32
TYPE0
READONLYF
REGISTER
ar5
WIDTH32
TYPE0
READONLYF
REGISTER
ar6
WIDTH32
TYPE0
READONLYF
REGISTER
ar7
WIDTH32
TYPE0
READONLYF
REGISTER
ar8
WIDTH32
TYPE0
READONLYF
REGISTER
ar9
WIDTH32
TYPE0
READONLYF
REGISTER
ar10
WIDTH32
TYPE0
READONLYF
REGISTER
ar11
WIDTH32
TYPE0
READONLYF
REGISTER
ar12
WIDTH32
TYPE0
READONLYF
REGISTER
ar13
WIDTH32
TYPE0
READONLYF
REGISTER
ar14
WIDTH32
TYPE0
READONLYF
REGISTER
ar15
WIDTH32
TYPE0
READONLYF
REGISTER
windowbase
WIDTH32
TYPE0
READONLYF
REGISTER
windowstart
WIDTH32
TYPE0
READONLYF

FILEVERSION

_version

MAJOR1
MINOR0


Component Description for TensilicaDiamond/DC_B_212GP.xml

PROCESSOR

DC_B_212GP

ENDIANeither
ELFCODE94
ATTRIBUTETABLEmodelAttrs
LIBRARYprocessor
LOADPHYSICALF
IMAGEFILEmodel
GDBPATH${XTENSA_BIN}/xt-gdb
GDBFLAGS--xtensa-core=DC_B_212GP
SIGNATURE0
VENDORovpworld.org
VERSION1.0
LicenseOpen Source Apache 2.0
DescriptionTensilica (RevB Silicon) DC_B_212GP ISS integration.
LimitationsDoes not currently support debug.

BUSMASTERPORT

INSTRUCTION

ADDRESSWIDTH32
MUSTBECONNECTEDF

BUSMASTERPORT

DATA

ADDRESSWIDTH32
MUSTBECONNECTEDF

REGISTERS

registers

REGISTER
mr0
WIDTH32
TYPE4
READONLYT
REGISTER
mr1
WIDTH32
TYPE2
READONLYF
REGISTER
mr2
WIDTH32
TYPE3
READONLYF
REGISTER
mr3
WIDTH32
TYPE0
READONLYF
REGISTER
lbeg
WIDTH32
TYPE0
READONLYF
REGISTER
lend
WIDTH32
TYPE0
READONLYF
REGISTER
lcount
WIDTH32
TYPE0
READONLYF
REGISTER
acclo
WIDTH32
TYPE0
READONLYF
REGISTER
acchi
WIDTH32
TYPE0
READONLYF
REGISTER
sar
WIDTH32
TYPE0
READONLYF
REGISTER
litbaddr
WIDTH32
TYPE0
READONLYF
REGISTER
ps
WIDTH32
TYPE0
READONLYF
REGISTER
scompare1
WIDTH32
TYPE0
READONLYF
REGISTER
expstate
WIDTH32
TYPE0
READONLYF
REGISTER
pc
WIDTH32
TYPE1
READONLYF
REGISTER
ar0
WIDTH32
TYPE0
READONLYF
REGISTER
ar1
WIDTH32
TYPE0
READONLYF
REGISTER
ar2
WIDTH32
TYPE0
READONLYF
REGISTER
ar3
WIDTH32
TYPE0
READONLYF
REGISTER
ar4
WIDTH32
TYPE0
READONLYF
REGISTER
ar5
WIDTH32
TYPE0
READONLYF
REGISTER
ar6
WIDTH32
TYPE0
READONLYF
REGISTER
ar7
WIDTH32
TYPE0
READONLYF
REGISTER
ar8
WIDTH32
TYPE0
READONLYF
REGISTER
ar9
WIDTH32
TYPE0
READONLYF
REGISTER
ar10
WIDTH32
TYPE0
READONLYF
REGISTER
ar11
WIDTH32
TYPE0
READONLYF
REGISTER
ar12
WIDTH32
TYPE0
READONLYF
REGISTER
ar13
WIDTH32
TYPE0
READONLYF
REGISTER
ar14
WIDTH32
TYPE0
READONLYF
REGISTER
ar15
WIDTH32
TYPE0
READONLYF
REGISTER
windowbase
WIDTH32
TYPE0
READONLYF
REGISTER
windowstart
WIDTH32
TYPE0
READONLYF

FILEVERSION

_version

MAJOR1
MINOR0


Component Description for TensilicaDiamond/DC_B_232L.xml

PROCESSOR

DC_B_232L

ENDIANeither
ELFCODE94
ATTRIBUTETABLEmodelAttrs
LIBRARYprocessor
LOADPHYSICALF
IMAGEFILEmodel
GDBPATH${XTENSA_BIN}/xt-gdb
GDBFLAGS--xtensa-core=DC_B_232L
SIGNATURE0
VENDORovpworld.org
VERSION1.0
LicenseOpen Source Apache 2.0
DescriptionTensilica (RevB Silicon) DC_B_232L ISS integration.
LimitationsDoes not currently support debug.

BUSMASTERPORT

INSTRUCTION

ADDRESSWIDTH32
MUSTBECONNECTEDF

BUSMASTERPORT

DATA

ADDRESSWIDTH32
MUSTBECONNECTEDF

REGISTERS

registers

REGISTER
mr0
WIDTH32
TYPE4
READONLYT
REGISTER
mr1
WIDTH32
TYPE2
READONLYF
REGISTER
mr2
WIDTH32
TYPE3
READONLYF
REGISTER
mr3
WIDTH32
TYPE0
READONLYF
REGISTER
lbeg
WIDTH32
TYPE0
READONLYF
REGISTER
lend
WIDTH32
TYPE0
READONLYF
REGISTER
lcount
WIDTH32
TYPE0
READONLYF
REGISTER
acclo
WIDTH32
TYPE0
READONLYF
REGISTER
acchi
WIDTH32
TYPE0
READONLYF
REGISTER
sar
WIDTH32
TYPE0
READONLYF
REGISTER
litbaddr
WIDTH32
TYPE0
READONLYF
REGISTER
ps
WIDTH32
TYPE0
READONLYF
REGISTER
scompare1
WIDTH32
TYPE0
READONLYF
REGISTER
expstate
WIDTH32
TYPE0
READONLYF
REGISTER
pc
WIDTH32
TYPE1
READONLYF
REGISTER
ar0
WIDTH32
TYPE0
READONLYF
REGISTER
ar1
WIDTH32
TYPE0
READONLYF
REGISTER
ar2
WIDTH32
TYPE0
READONLYF
REGISTER
ar3
WIDTH32
TYPE0
READONLYF
REGISTER
ar4
WIDTH32
TYPE0
READONLYF
REGISTER
ar5
WIDTH32
TYPE0
READONLYF
REGISTER
ar6
WIDTH32
TYPE0
READONLYF
REGISTER
ar7
WIDTH32
TYPE0
READONLYF
REGISTER
ar8
WIDTH32
TYPE0
READONLYF
REGISTER
ar9
WIDTH32
TYPE0
READONLYF
REGISTER
ar10
WIDTH32
TYPE0
READONLYF
REGISTER
ar11
WIDTH32
TYPE0
READONLYF
REGISTER
ar12
WIDTH32
TYPE0
READONLYF
REGISTER
ar13
WIDTH32
TYPE0
READONLYF
REGISTER
ar14
WIDTH32
TYPE0
READONLYF
REGISTER
ar15
WIDTH32
TYPE0
READONLYF
REGISTER
windowbase
WIDTH32
TYPE0
READONLYF
REGISTER
windowstart
WIDTH32
TYPE0
READONLYF

FILEVERSION

_version

MAJOR1
MINOR0


Component Description for TensilicaDiamond/DC_B_330HiFi.xml

PROCESSOR

DC_B_330HiFi

ENDIANeither
ELFCODE94
ATTRIBUTETABLEmodelAttrs
LIBRARYprocessor
LOADPHYSICALF
IMAGEFILEmodel
GDBPATH${XTENSA_BIN}/xt-gdb
GDBFLAGS--xtensa-core=DC_B_330HiFi
SIGNATURE0
VENDORovpworld.org
VERSION1.0
LicenseOpen Source Apache 2.0
DescriptionTensilica (RevB Silicon) DC_B_330HiFi ISS integration.
LimitationsDoes not currently support debug.

BUSMASTERPORT

INSTRUCTION

ADDRESSWIDTH32
MUSTBECONNECTEDF

BUSMASTERPORT

DATA

ADDRESSWIDTH32
MUSTBECONNECTEDF

REGISTERS

registers

REGISTER
mr0
WIDTH32
TYPE4
READONLYT
REGISTER
mr1
WIDTH32
TYPE2
READONLYF
REGISTER
mr2
WIDTH32
TYPE3
READONLYF
REGISTER
mr3
WIDTH32
TYPE0
READONLYF
REGISTER
lbeg
WIDTH32
TYPE0
READONLYF
REGISTER
lend
WIDTH32
TYPE0
READONLYF
REGISTER
lcount
WIDTH32
TYPE0
READONLYF
REGISTER
acclo
WIDTH32
TYPE0
READONLYF
REGISTER
acchi
WIDTH32
TYPE0
READONLYF
REGISTER
sar
WIDTH32
TYPE0
READONLYF
REGISTER
litbaddr
WIDTH32
TYPE0
READONLYF
REGISTER
ps
WIDTH32
TYPE0
READONLYF
REGISTER
scompare1
WIDTH32
TYPE0
READONLYF
REGISTER
expstate
WIDTH32
TYPE0
READONLYF
REGISTER
pc
WIDTH32
TYPE1
READONLYF
REGISTER
ar0
WIDTH32
TYPE0
READONLYF
REGISTER
ar1
WIDTH32
TYPE0
READONLYF
REGISTER
ar2
WIDTH32
TYPE0
READONLYF
REGISTER
ar3
WIDTH32
TYPE0
READONLYF
REGISTER
ar4
WIDTH32
TYPE0
READONLYF
REGISTER
ar5
WIDTH32
TYPE0
READONLYF
REGISTER
ar6
WIDTH32
TYPE0
READONLYF
REGISTER
ar7
WIDTH32
TYPE0
READONLYF
REGISTER
ar8
WIDTH32
TYPE0
READONLYF
REGISTER
ar9
WIDTH32
TYPE0
READONLYF
REGISTER
ar10
WIDTH32
TYPE0
READONLYF
REGISTER
ar11
WIDTH32
TYPE0
READONLYF
REGISTER
ar12
WIDTH32
TYPE0
READONLYF
REGISTER
ar13
WIDTH32
TYPE0
READONLYF
REGISTER
ar14
WIDTH32
TYPE0
READONLYF
REGISTER
ar15
WIDTH32
TYPE0
READONLYF
REGISTER
windowbase
WIDTH32
TYPE0
READONLYF
REGISTER
windowstart
WIDTH32
TYPE0
READONLYF

FILEVERSION

_version

MAJOR1
MINOR0


Component Description for TensilicaDiamond/DC_B_545CK.xml

PROCESSOR

DC_B_545CK

ENDIANeither
ELFCODE94
ATTRIBUTETABLEmodelAttrs
LIBRARYprocessor
LOADPHYSICALF
IMAGEFILEmodel
GDBPATH${XTENSA_BIN}/xt-gdb
GDBFLAGS--xtensa-core=DC_B_545CK
SIGNATURE0
VENDORovpworld.org
VERSION1.0
LicenseOpen Source Apache 2.0
DescriptionTensilica (RevB Silicon) DC_B_545CK ISS integration.
LimitationsDoes not currently support debug.

FIFOPORT

IPQ

MUSTBECONNECTEDF
TYPEinput

FIFOPORT

OPQ

MUSTBECONNECTEDF
TYPEoutput

BUSMASTERPORT

INSTRUCTION

ADDRESSWIDTH32
MUSTBECONNECTEDF

BUSMASTERPORT

DATA

ADDRESSWIDTH32
MUSTBECONNECTEDF

REGISTERS

registers

REGISTER
mr0
WIDTH32
TYPE4
READONLYT
REGISTER
mr1
WIDTH32
TYPE2
READONLYF
REGISTER
mr2
WIDTH32
TYPE3
READONLYF
REGISTER
mr3
WIDTH32
TYPE0
READONLYF
REGISTER
lbeg
WIDTH32
TYPE0
READONLYF
REGISTER
lend
WIDTH32
TYPE0
READONLYF
REGISTER
lcount
WIDTH32
TYPE0
READONLYF
REGISTER
acclo
WIDTH32
TYPE0
READONLYF
REGISTER
acchi
WIDTH32
TYPE0
READONLYF
REGISTER
sar
WIDTH32
TYPE0
READONLYF
REGISTER
litbaddr
WIDTH32
TYPE0
READONLYF
REGISTER
ps
WIDTH32
TYPE0
READONLYF
REGISTER
scompare1
WIDTH32
TYPE0
READONLYF
REGISTER
expstate
WIDTH32
TYPE0
READONLYF
REGISTER
pc
WIDTH32
TYPE1
READONLYF
REGISTER
ar0
WIDTH32
TYPE0
READONLYF
REGISTER
ar1
WIDTH32
TYPE0
READONLYF
REGISTER
ar2
WIDTH32
TYPE0
READONLYF
REGISTER
ar3
WIDTH32
TYPE0
READONLYF
REGISTER
ar4
WIDTH32
TYPE0
READONLYF
REGISTER
ar5
WIDTH32
TYPE0
READONLYF
REGISTER
ar6
WIDTH32
TYPE0
READONLYF
REGISTER
ar7
WIDTH32
TYPE0
READONLYF
REGISTER
ar8
WIDTH32
TYPE0
READONLYF
REGISTER
ar9
WIDTH32
TYPE0
READONLYF
REGISTER
ar10
WIDTH32
TYPE0
READONLYF
REGISTER
ar11
WIDTH32
TYPE0
READONLYF
REGISTER
ar12
WIDTH32
TYPE0
READONLYF
REGISTER
ar13
WIDTH32
TYPE0
READONLYF
REGISTER
ar14
WIDTH32
TYPE0
READONLYF
REGISTER
ar15
WIDTH32
TYPE0
READONLYF
REGISTER
windowbase
WIDTH32
TYPE0
READONLYF
REGISTER
windowstart
WIDTH32
TYPE0
READONLYF

FILEVERSION

_version

MAJOR1
MINOR0


Component Description for TensilicaDiamond/DC_B_570T.xml

PROCESSOR

DC_B_570T

ENDIANeither
ELFCODE94
ATTRIBUTETABLEmodelAttrs
LIBRARYprocessor
LOADPHYSICALF
IMAGEFILEmodel
GDBPATH${XTENSA_BIN}/xt-gdb
GDBFLAGS--xtensa-core=DC_B_108mini
SIGNATURE0
VENDORovpworld.org
VERSION1.0
LicenseOpen Source Apache 2.0
DescriptionTensilica (RevB Silicon) DC_B_570T ISS integration.
LimitationsDoes not currently support debug.

FIFOPORT

IPQ

MUSTBECONNECTEDF
TYPEinput

FIFOPORT

OPQ

MUSTBECONNECTEDF
TYPEoutput

BUSMASTERPORT

INSTRUCTION

ADDRESSWIDTH32
MUSTBECONNECTEDF

BUSMASTERPORT

DATA

ADDRESSWIDTH32
MUSTBECONNECTEDF

REGISTERS

registers

REGISTER
mr0
WIDTH32
TYPE4
READONLYT
REGISTER
mr1
WIDTH32
TYPE2
READONLYF
REGISTER
mr2
WIDTH32
TYPE3
READONLYF
REGISTER
mr3
WIDTH32
TYPE0
READONLYF
REGISTER
lbeg
WIDTH32
TYPE0
READONLYF
REGISTER
lend
WIDTH32
TYPE0
READONLYF
REGISTER
lcount
WIDTH32
TYPE0
READONLYF
REGISTER
acclo
WIDTH32
TYPE0
READONLYF
REGISTER
acchi
WIDTH32
TYPE0
READONLYF
REGISTER
sar
WIDTH32
TYPE0
READONLYF
REGISTER
litbaddr
WIDTH32
TYPE0
READONLYF
REGISTER
ps
WIDTH32
TYPE0
READONLYF
REGISTER
scompare1
WIDTH32
TYPE0
READONLYF
REGISTER
expstate
WIDTH32
TYPE0
READONLYF
REGISTER
pc
WIDTH32
TYPE1
READONLYF
REGISTER
ar0
WIDTH32
TYPE0
READONLYF
REGISTER
ar1
WIDTH32
TYPE0
READONLYF
REGISTER
ar2
WIDTH32
TYPE0
READONLYF
REGISTER
ar3
WIDTH32
TYPE0
READONLYF
REGISTER
ar4
WIDTH32
TYPE0
READONLYF
REGISTER
ar5
WIDTH32
TYPE0
READONLYF
REGISTER
ar6
WIDTH32
TYPE0
READONLYF
REGISTER
ar7
WIDTH32
TYPE0
READONLYF
REGISTER
ar8
WIDTH32
TYPE0
READONLYF
REGISTER
ar9
WIDTH32
TYPE0
READONLYF
REGISTER
ar10
WIDTH32
TYPE0
READONLYF
REGISTER
ar11
WIDTH32
TYPE0
READONLYF
REGISTER
ar12
WIDTH32
TYPE0
READONLYF
REGISTER
ar13
WIDTH32
TYPE0
READONLYF
REGISTER
ar14
WIDTH32
TYPE0
READONLYF
REGISTER
ar15
WIDTH32
TYPE0
READONLYF
REGISTER
windowbase
WIDTH32
TYPE0
READONLYF
REGISTER
windowstart
WIDTH32
TYPE0
READONLYF

FILEVERSION

_version

MAJOR1
MINOR0


Component Description for TensilicaDiamond/DC_B_570T_2.xml

HW

robustConstitution

BUS

bus2

ADDRESSWIDTH32

MEMORYINSTANCE

memory2

VLNVREFERENCE
ram
BUSSLAVEPORTCONNECTION
sp1
CONNECTIONbus2
HIADDRESS0xffffffff
LOADDRESS0x0

PROCESSORINSTANCE

appProc2

ID1
IMAGEFILEconstitutionIn.exe
TRAP0
ENDIANlittle
VLNVREFERENCE
DC_B_570T
BUSMASTERPORTCONNECTION
INSTRUCTION
CONNECTIONbus2
HIADDRESS0xffffffff
LOADDRESS0x0
BUSMASTERPORTCONNECTION
DATA
CONNECTIONbus2
HIADDRESS0xffffffff
LOADDRESS0x0
FIFOPORTCONNECTION
IPQ
CONNECTIONfifo1

BUS

bus1

ADDRESSWIDTH32

FIFO

fifo1

WIDTH32
DEPTH7

MEMORYINSTANCE

memory1

VLNVREFERENCE
ram
BUSSLAVEPORTCONNECTION
sp1
CONNECTIONbus1
HIADDRESS0xffffffff
LOADDRESS0x0

PROCESSORINSTANCE

appProc1

ID0
IMAGEFILEconstitutionOut.exe
SIMULATEEXCEPTIONSF
TRAP0
ENDIANlittle
VLNVREFERENCE
DC_B_570T
BUSMASTERPORTCONNECTION
INSTRUCTION
CONNECTIONbus1
HIADDRESS0xffffffff
LOADDRESS0x0
BUSMASTERPORTCONNECTION
DATA
CONNECTIONbus1
HIADDRESS0xffffffff
LOADDRESS0x0
FIFOPORTCONNECTION
OPQ
CONNECTIONfifo1

FILEVERSION

_version

MAJOR1
MINOR0


Component Description for TensilicaDiamond/diamondCore.model.xml

PROCESSOR

TensilicaDiamondCore

ENDIANeither
ELFCODE94
ATTRIBUTETABLEmodelAttrs
LIBRARYprocessor
LOADPHYSICALF
IMAGEFILEmodel
GDBPATH${XTENSA_BIN}/xt-gdb
GDBFLAGS--xtensa-core=${XTENSA_CORE}
SIGNATURE0
VENDORovpworld.org
VERSION1.0
LicenseOpen Source Apache 2.0
DescriptionTensilica DiamondCore ISS integration. Supports cores Version A silicon DC_108mini, DC_212GP, DC_232L, DC_330HiFi, DC_545CK, DC_570T. Version B silicon DC_B_106micro, DC_B_108mini, DC_B_212GP, DC_B_232L, DC_B_330HiFi, DC_B_545CK, DC_B_570T


Component Description for TensilicaDiamond/tensilica.model.xml

PROCESSOR

tensilica

ENDIANeither
ELFCODE94
ATTRIBUTETABLEmodelAttrs
LIBRARYprocessor
LOADPHYSICALF
IMAGEFILEmodel
SIGNATURE0
VENDORovpworld.org
VERSION1.0
LicenseOpen Source Apache 2.0
DescriptionTensilica DiamondCores ISS integration. Supports Version A silicon cores DC_108mini, DC_212GP, DC_232L, DC_330HiFi, DC_545CK, DC_570T and Version B silicon cores DC_B_106micro, DC_B_108mini, DC_B_212GP, DC_B_232L, DC_B_330HiFi, DC_B_545CK, DC_B_570T.
LimitationsDoes not currently support debug.

BUSMASTERPORT

INSTRUCTION

ADDRESSWIDTH32
MUSTBECONNECTEDF

BUSMASTERPORT

DATA

ADDRESSWIDTH32
MUSTBECONNECTEDF

REGISTERS

registers

REGISTER
mr0
WIDTH32
TYPE4
READONLYT
REGISTER
mr1
WIDTH32
TYPE2
READONLYF
REGISTER
mr2
WIDTH32
TYPE3
READONLYF
REGISTER
mr3
WIDTH32
TYPE0
READONLYF
REGISTER
lbeg
WIDTH32
TYPE0
READONLYF
REGISTER
lend
WIDTH32
TYPE0
READONLYF
REGISTER
lcount
WIDTH32
TYPE0
READONLYF
REGISTER
acclo
WIDTH32
TYPE0
READONLYF
REGISTER
acchi
WIDTH32
TYPE0
READONLYF
REGISTER
sar
WIDTH32
TYPE0
READONLYF
REGISTER
litbaddr
WIDTH32
TYPE0
READONLYF
REGISTER
ps
WIDTH32
TYPE0
READONLYF
REGISTER
scompare1
WIDTH32
TYPE0
READONLYF
REGISTER
expstate
WIDTH32
TYPE0
READONLYF
REGISTER
pc
WIDTH32
TYPE1
READONLYF
REGISTER
ar0
WIDTH32
TYPE0
READONLYF
REGISTER
ar1
WIDTH32
TYPE0
READONLYF
REGISTER
ar2
WIDTH32
TYPE0
READONLYF
REGISTER
ar3
WIDTH32
TYPE0
READONLYF
REGISTER
ar4
WIDTH32
TYPE0
READONLYF
REGISTER
ar5
WIDTH32
TYPE0
READONLYF
REGISTER
ar6
WIDTH32
TYPE0
READONLYF
REGISTER
ar7
WIDTH32
TYPE0
READONLYF
REGISTER
ar8
WIDTH32
TYPE0
READONLYF
REGISTER
ar9
WIDTH32
TYPE0
READONLYF
REGISTER
ar10
WIDTH32
TYPE0
READONLYF
REGISTER
ar11
WIDTH32
TYPE0
READONLYF
REGISTER
ar12
WIDTH32
TYPE0
READONLYF
REGISTER
ar13
WIDTH32
TYPE0
READONLYF
REGISTER
ar14
WIDTH32
TYPE0
READONLYF
REGISTER
ar15
WIDTH32
TYPE0
READONLYF
REGISTER
windowbase
WIDTH32
TYPE0
READONLYF
REGISTER
windowstart
WIDTH32
TYPE0
READONLYF

FILEVERSION

_version

MAJOR1
MINOR0


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