VinRZ5110 Processor Model was developed based on Imperas? morphing technology and runs under the OVPSim Windows platform.
VinRZ5110 Processor Key Features
Key features of
VinRZ5110 Processor are:
1. 32-bit, 5-stage pipeline, Harvard Architecture RISC CPU
2. Five operating modes with optimized shadow register bank structure
- Supports very fast context switching for high priority interrupt modes
3. Single cycle 32X16 MAC enabling convergence of RISC and DSP
4. Native bus interface support for on-chip peripherals
- Realizes low interrupt latencies
5. Memory copy, atomic memory access, semaphore instructions
- Improves code density by a large margin
6. Low Power Modes support
- Power-down mode (triggered by en_idle instruction)
- Supports low power modes that facilitate CE designs
Downloads
| DOWNLOAD VinRZ5110 model with example platform and application OVP_Release_1.01.zip / 33.5 MB |
OVP_Release_1.01 Details
OVP_Release_1.01 consists of the complete toolchain binaries for
VinRZ5110 ISA and the
VinRZ5110
Processor model executable.
Toolchain was build under cygwin ported 32-bit Windows platform. Extract the vinrz_tool_chain tarball and
move the binaries to the "/usr/local" directory.
VinRZ5110_Model was build in the OVPSim simulator environment. The User Guide explains briefly about
"HOW TO USE" the
VinRZ5110 Processor Model in the OVPSim windows platform with example.
NOTE: Available in the files section is the zip file
VinRZ5110.zip that contains the
VinRZ5110 model source code updated to the current OVP release by OVP. All other downloads are maintained by
VinChip Systems.
Component Description for VinRZ5110/VinRZ5110.igen.xml
PROCESSOR | VinRZ5110 |
ELFCODE | 0 |
ENDIAN | little |
FAMILY | Vinchip |
IMAGEFILE | model |
LIBRARY | processor |
PROCDOC | $IMPERAS_HOME/ImperasLib/source/vinchip.com/processor/VinRZ5110/1.0/doc/OVP_Model_Specific_Information_VinRZ5110_generic.pdf |
RELEASESTATUS | 2 |
USEINDEFAULTPLATFORM | T |
VENDOR | vinchip.com |
VERSION | 1.0 |
VISIBILITY | 0 |
FORMALATTRIBUTE | variant |
TYPE | enumeration |
DOCSECTION | doc |
TEXT | Description |
DOCTEXT | txt |
TEXT | Processor variant |
ENUM | vinRZ5110 |
VALUE | 0 |
DOCSECTION | doc |
TEXT | Description |
DOCTEXT | txt |
TEXT | Single default variant |
BUSMASTERPORT | INSTRUCTION |
ADDRESSWIDTH | 32 |
ADDRESSWIDTHMAX | 32 |
ADDRESSWIDTHMIN | 32 |
MUSTBECONNECTED | T |
DOCSECTION | doc |
TEXT | Description |
DOCTEXT | txt |
TEXT | Used to fetch code for execution |
BUSMASTERPORT | DATA |
ADDRESSWIDTH | 32 |
ADDRESSWIDTHMAX | 32 |
ADDRESSWIDTHMIN | 32 |
MUSTBECONNECTED | F |
DOCSECTION | doc |
TEXT | Description |
DOCTEXT | txt |
TEXT | Used to read & write data |
COMMAND | isync |
DOCSECTION | doc |
TEXT | Description |
DOCTEXT | txt |
TEXT | specify instruction address range for synchronous execution |
COMMANDARG | addresshi |
TYPE | Uns64 |
DOCSECTION | doc |
TEXT | Description |
DOCTEXT | txt |
TEXT | end address of synchronous execution range |
COMMANDARG | addresslo |
TYPE | Uns64 |
DOCSECTION | doc |
TEXT | Description |
DOCTEXT | txt |
TEXT | start address of synchronous execution range |
COMMAND | itrace |
DOCSECTION | doc |
TEXT | Description |
DOCTEXT | txt |
TEXT | enable or disable instruction tracing |
COMMANDARG | access |
TYPE | String |
DOCSECTION | doc |
TEXT | Description |
DOCTEXT | txt |
TEXT | show memory accesses by this instruction. Argument can be any combination of X (execute), A (load or store access) and S (system) |
COMMANDARG | after |
TYPE | Uns64 |
DOCSECTION | doc |
TEXT | Description |
DOCTEXT | txt |
TEXT | apply after this many instructions |
COMMANDARG | enable |
TYPE | Boolean |
DOCSECTION | doc |
TEXT | Description |
DOCTEXT | txt |
TEXT | enable instruction tracing |
COMMANDARG | full |
TYPE | Boolean |
DOCSECTION | doc |
TEXT | Description |
DOCTEXT | txt |
TEXT | turn on all trace features |
COMMANDARG | instructioncount |
TYPE | Boolean |
DOCSECTION | doc |
TEXT | Description |
DOCTEXT | txt |
TEXT | include the instruction number in each trace |
COMMANDARG | memory |
TYPE | String |
DOCSECTION | doc |
TEXT | Description |
DOCTEXT | txt |
TEXT | (Alias for access). show memory accesses by this instruction. Argument can be any combination of X (execute), A (load or store access) and S (system) |
COMMANDARG | mode |
TYPE | Boolean |
DOCSECTION | doc |
TEXT | Description |
DOCTEXT | txt |
TEXT | show processor mode changes |
COMMANDARG | off |
TYPE | Boolean |
DOCSECTION | doc |
TEXT | Description |
DOCTEXT | txt |
TEXT | disable instruction tracing |
COMMANDARG | on |
TYPE | Boolean |
DOCSECTION | doc |
TEXT | Description |
DOCTEXT | txt |
TEXT | enable instruction tracing |
COMMANDARG | processorname |
TYPE | Boolean |
DOCSECTION | doc |
TEXT | Description |
DOCTEXT | txt |
TEXT | Include processor name in all trace lines |
COMMANDARG | registerchange |
TYPE | Boolean |
DOCSECTION | doc |
TEXT | Description |
DOCTEXT | txt |
TEXT | show registers changed by this instruction |
COMMANDARG | registers |
TYPE | Boolean |
DOCSECTION | doc |
TEXT | Description |
DOCTEXT | txt |
TEXT | show registers after each trace |
FILEVERSION | _version_0 |
MAJOR | 1 |
MINOR | 0 |
CategoryProcessor VinChipSystems
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