OVP Virtual Platform: XilinxML505
This page provides detailed information about the OVP Virtual Platform Model of the
xilinx.ovpworld.org XilinxML505 platform.
Description
Xilinx ML505 Reference Platform
Licensing
Open Source Apache 2.0
Limitations
This platform provides a subset of the full platform functionality. It is provided to boot the Linux operating system.
Other software may be used but the operation cannot be guaranteed.
Platform capable of booting linux
Reference
UG347 (v3.1.2) May 16, 2011
Location
The XilinxML505 virtual platform is located in an Imperas/OVP installation at the VLNV: xilinx.ovpworld.org / module / XilinxML505 / 1.0.
Platform Summary
Table : Components in platform
Processor [xilinx.ovpworld.org/processor/microblaze/1.0] instance: microblaze_0
Instance Parameters
Several parameters can be specified when a processor is instanced in a platform. For this processor instance 'microblaze_0' it has been instanced with the following parameters:
Table 1: Processor Instance 'microblaze_0' Parameters (Configurations)
Parameter | Value | Description |
---|
endian | big | Select processor endian (big or little) |
simulateexceptions | simulateexceptions | Causes the processor simulate exceptions instead of halting |
mips | 125 | The nominal MIPS for the processor |
Table 2: Processor Instance 'microblaze_0' Parameters (Attributes)
Parameter Name | Value | Type |
---|
C_USE_MMU | 3 | uns32 |
C_MMU_ITLB_SIZE | 2 | uns32 |
C_MMU_DTLB_SIZE | 4 | uns32 |
C_MMU_TLB_ACCESS | 3 | uns32 |
C_MMU_ZONES | 16 | uns32 |
C_USE_EXTENDED_FSL_INSTR | 1 | bool |
C_FSL_EXCEPTION | 1 | bool |
C_USE_HW_MUL | 2 | uns32 |
C_PVR | 2 | uns32 |
C_OPCODE_0x0_ILLEGAL | 1 | bool |
C_FPU_EXCEPTION | 1 | bool |
C_UNALIGNED_EXCEPTIONS | 1 | bool |
C_ILL_OPCODE_EXCEPTION | 1 | bool |
C_DIV_ZERO_EXCEPTION | 1 | bool |
C_INTERCONNECT | 1 | uns32 |
C_USE_BARREL | 1 | bool |
C_USE_DIV | 1 | bool |
C_FSL_LINKS | 4 | uns32 |
C_DEBUG_ENABLED | 1 | bool |
C_I_LMB | 1 | bool |
C_D_LMB | 1 | bool |
C_USE_FPU | 2 | Uns32 |
C_USE_MSR_INSTR | 1 | bool |
C_USE_PCMP_INSTR | 1 | bool |
C_FAMILY | 12 | uns32 |
Memory Map for processor 'microblaze_0' bus: 'bus1'
Processor instance 'microblaze_0' is connected to bus 'bus1' using master port 'INSTRUCTION'.
Processor instance 'microblaze_0' is connected to bus 'bus1' using master port 'DATA'.
Table 3: Memory Map ( 'microblaze_0' / 'bus1' [width: 32] )
Lo Address | Hi Address | Instance | Component |
---|
0x0 | 0x1FFFFFF | BOOTMEM | ram |
0x81400000 | 0x8140FFFF | LEDs_8Bit | xps-gpio |
0x81600000 | 0x8160FFFF | IIC_EEPROM | xps-iic |
0x81800000 | 0x8180001F | xps_intc_0 | xps-intc |
0x81C00000 | 0x81C0003F | Hard_Ethernet_MAC | xps-ll-temac |
0x83600000 | 0x8360FFFF | SysACE_CompactFlash | xps-sysace |
0x83C00000 | 0x83C0001F | xps_timer_1 | xps-timer |
0x84000000 | 0x8400000F | RS232_Uart_1 | xps-uartlite |
0x84400000 | 0x8440FFFF | debug_module | mdm |
0x84600180 | 0x846001FF | mpmc | mpmc |
0x8FFFF000 | 0x8FFFFFFF | UNKNOWN_PERIPH | ram |
0x90000000 | 0x9FFFFFFF | DDR2_SDRAM | ram |
0xA0000000 | 0xA1FFFFFF | mb_plb | xps-mch-emc |
Net Connections to processor: 'microblaze_0'
Table 4: Processor Net Connections ( 'microblaze_0' )
Net Port | Net | Instance | Component |
---|
Interrupt | Interrupt_net | xps_intc_0 | xps-intc |
Peripheral Instances
Peripheral [xilinx.ovpworld.org/peripheral/xps-gpio/1.0] instance: LEDs_8Bit
Description
Microblaze General Purpose IO
Licensing
Open Source Apache 2.0
Limitations
This model implements the registers but has no functional behavior
Reference
DS569 December 2, 2009 v2.00a
There are no configuration options set for this peripheral instance.
Peripheral [xilinx.ovpworld.org/peripheral/xps-iic/1.0] instance: IIC_EEPROM
Description
Microblaze IIC Bus Interface
Licensing
Open Source Apache 2.0
Limitations
This model implements the registers but has no functional behavior
Reference
DS606 June 22, 2011 v2.03a
There are no configuration options set for this peripheral instance.
Peripheral [xilinx.ovpworld.org/peripheral/xps-intc/1.0] instance: xps_intc_0
Description
Microblaze LogiCORE IP XPS Interrupt Controller
Licensing
Open Source Apache 2.0
Limitations
This model implements all of the required behavior sufficient to boot Linux
Reference
DS572 April 19, 2010 v2.01a
There are no configuration options set for this peripheral instance.
Peripheral [xilinx.ovpworld.org/peripheral/xps-ll-temac/1.0] instance: Hard_Ethernet_MAC
Description
Microblaze LogiCORE IP XPS LL TEMAC Ethernet Core
Licensing
Open Source Apache 2.0
Limitations
This model implements the registers but has no functional behavior
Reference
DS537 December 14, 2010 v2.03a
There are no configuration options set for this peripheral instance.
Peripheral [xilinx.ovpworld.org/peripheral/xps-sysace/1.0] instance: SysACE_CompactFlash
Description
Microblaze LogiCORE SYSACE Interface Controller
Licensing
Open Source Apache 2.0
Limitations
This model implements the registers but has no functional behavior
Reference
DS583 December 2, 2009 v1.01a
There are no configuration options set for this peripheral instance.
Peripheral [xilinx.ovpworld.org/peripheral/xps-timer/1.0] instance: xps_timer_1
Description
Microblaze LogiCORE IP XPS Timer/Counter
Licensing
Open Source Apache 2.0
Limitations
Resolution of this timer is limited to the simulation time slice (aka quantum) size
Reference
DS573 April 19, 2010 v1.02a
There are no configuration options set for this peripheral instance.
Peripheral [xilinx.ovpworld.org/peripheral/xps-uartlite/1.0] instance: RS232_Uart_1
Description
Xilinx Uart-Lite
Limitations
Register Accurate & Functional Model
Licensing
Open Source Apache 2.0
Reference
DS573 Jun 22, 2011 v1.02.a
Table 5: Configuration options (attributes) set for instance 'RS232_Uart_1'
Attributes | Value |
---|
outfile | RS232_Uart_1.log |
finishOnDisconnect | 1 |
Peripheral [xilinx.ovpworld.org/peripheral/mdm/1.0] instance: debug_module
Description
Microblaze Debug Module
Licensing
Open Source Apache 2.0
Limitations
This model implements the registers but has no functional behavior
Reference
DS641 July 23, 2010 v2.00.a
There are no configuration options set for this peripheral instance.
Peripheral [xilinx.ovpworld.org/peripheral/mpmc/1.0] instance: mpmc
Description
Microblaze Multi-Port Memory Controller
Licensing
Open Source Apache 2.0
Limitations
This model implements the registers but has no functional behavior
Reference
DS643 March 1, 2011 v6.03.a
There are no configuration options set for this peripheral instance.
Peripheral [xilinx.ovpworld.org/peripheral/xps-mch-emc/1.0] instance: mb_plb
Description
Microblaze LogiCORE IP XPS MCH EMC Multi Channel External Memory Controller
Licensing
Open Source Apache 2.0
Limitations
This model implements the registers but has no functional behavior
Reference
DS575 June 22, 2010 v3.01a
There are no configuration options set for this peripheral instance.