OVP Peripheral Model: XilinxXpsTimer
Model Specific Information
This page provides introductory usage information for an Imperas OVP peripheral behavioral model.
The page is split into sections providing specific information for this peripheral,
including any ports for connecting into a platform, registers, other component parts, and configuration options and general information for peripheral modeling with Imperas OVP.
Description
Microblaze LogiCORE IP XPS Timer/Counter
Licensing
Open Source Apache 2.0
Limitations
Resolution of this timer is limited to the simulation time slice (aka quantum) size
Reference
DS573 April 19, 2010 v1.02a
Location
The xps-timer peripheral model is located in an Imperas/OVP installation at the VLNV: xilinx.ovpworld.org / peripheral / xps-timer / 1.0.
Peripheral Instance Parameters
This model accepts the following parameters:
Table : Peripheral Parameters
Name | Type | Description |
---|
frequency | uns32 | Specify frequency of the counters in Hz (default 125000000 Hz) |
endian | string | Specify the endian of the processor interface (default big endian) |
Net Ports
This model has the following net ports:
Table 1: Net Ports
Name | Type | Must Be Connected | Description |
---|
Interrupt | output | F (False) | |
Bus Slave Ports
This model has the following bus slave ports:
Bus Slave Port: plb
Table 2: Bus Slave Port: plb
Name | Size (bytes) | Must Be Connected | Description |
---|
plb | 0x20 | T (True) | |
Table 3: Bus Slave Port: plb Registers:
Name | Offset | Width (bits) | Description | R/W | is Volatile |
---|
REG_TCSR0 | 0x0 | 32 | | | |
REG_TLR0 | 0x4 | 32 | | | |
REG_TCR0 | 0x8 | 32 | | | |
REG_TCSR1 | 0x10 | 32 | | | |
REG_TLR1 | 0x14 | 32 | | | |
REG_TCR1 | 0x18 | 32 | | | |
Platforms that use this peripheral component
Peripheral components can be used in many different platforms, including those developed by Imperas or by other users of OVP. You can use this peripheral in your own platforms.
Table 4: Publicly available platforms using peripheral 'xps-timer'