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XilinxXpsUartlite



OVP Peripheral Model: XilinxXpsUartlite



Model Specific Information

This page provides introductory usage information for an Imperas OVP peripheral behavioral model. The page is split into sections providing specific information for this peripheral, including any ports for connecting into a platform, registers, other component parts, and configuration options and general information for peripheral modeling with Imperas OVP.

Description

Xilinx Uart-Lite

Limitations

Register Accurate & Functional Model

Licensing

Open Source Apache 2.0

Reference

DS573 Jun 22, 2011 v1.02.a

Location

The xps-uartlite peripheral model is located in an Imperas/OVP installation at the VLNV: xilinx.ovpworld.org / peripheral / xps-uartlite / 1.0.



Peripheral Instance Parameters

This model accepts the following parameters:

Table : Peripheral Parameters

NameTypeDescription
endianstringSpecify the endian of the processor interface (default big endian)
consoleboolIf specified, port number is ignored, and a console pops up automatically
portnumuns32If set, listen on this port. If set to zero, allocate a port from the pool and listen on that.
infilestringName of file to use for device source
outfilestringName of file to write device output
portFilestringIf portnum was specified as zero, write the port number to this file when it's known
logboolIf specified, serial output will go to simulator log
finishOnDisconnectboolIf set, disconnecting the port will cause the simulation to finish
connectnonblockingboolIf set, simulation can begin before the connection is made
xcharsuns32Width of console in characters
ycharsuns32Height of console in characters
recordstringRecord external events into this file
replaystringReplay external events from this file



Net Ports

This model has the following net ports:

Table 1: Net Ports

NameTypeMust Be ConnectedDescription
InterruptoutputF (False)



Bus Slave Ports

This model has the following bus slave ports:

Bus Slave Port: plb

Table 2: Bus Slave Port: plb

NameSize (bytes)Must Be ConnectedDescription
plb0x10T (True)

Table 3: Bus Slave Port: plb Registers:

NameOffsetWidth (bits)DescriptionR/Wis Volatile
REG_RxFifo0x032
REG_TxFifo0x432
REG_Stat0x832
REG_Ctrl0xc32



Platforms that use this peripheral component

Peripheral components can be used in many different platforms, including those developed by Imperas or by other users of OVP. You can use this peripheral in your own platforms.

Table 4: Publicly available platforms using peripheral 'xps-uartlite'

Platform NameVendor
XilinxML505xilinx.ovpworld.org
Zynq_PL_TTELNoC_sensor_actor_node_public_demonstratorsafepower.ovpworld.org
XilinxML505xilinx.ovpworld.org



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