OVP Peripheral Model: XilinxZynq7000Can
Model Specific Information
This page provides introductory usage information for an Imperas OVP peripheral behavioral model.
The page is split into sections providing specific information for this peripheral,
including any ports for connecting into a platform, registers, other component parts, and configuration options and general information for peripheral modeling with Imperas OVP.
Description
Zynq 7000 CAN Registers
Licensing
Open Source Apache 2.0
Limitations
This model implements the full set of registers but no behavior.
Reference
Zynq-7000 TRM (https://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf)
Location
The zynq_7000-can peripheral model is located in an Imperas/OVP installation at the VLNV: xilinx.ovpworld.org / peripheral / zynq_7000-can / 1.0.
Net Ports
This model has the following net ports:
Table : Net Ports
Name | Type | Must Be Connected | Description |
---|
intOut | output | F (False) | |
Bus Slave Ports
This model has the following bus slave ports:
Bus Slave Port: bport1
Table 1: Bus Slave Port: bport1
Name | Size (bytes) | Must Be Connected | Description |
---|
bport1 | 0x1000 | T (True) | |
Table 2: Bus Slave Port: bport1 Registers:
Name | Offset | Width (bits) | Description | R/W | is Volatile |
---|
ab_SRR | 0x0 | 32 | Software Reset Register | | |
ab_MSR | 0x4 | 32 | Mode Select Register | | |
ab_BRPR | 0x8 | 32 | Baud Rate Prescaler Register | | |
ab_BTR | 0xc | 32 | Bit Timing Register | | |
ab_ECR | 0x10 | 32 | Error Counter Register | | |
ab_ESR | 0x14 | 32 | Error Status Register | | |
ab_SR | 0x18 | 32 | Status Register | | |
ab_ISR | 0x1c | 32 | Interrupt Status Register | | |
ab_IER | 0x20 | 32 | Interrupt Enable Register | | |
ab_ICR | 0x24 | 32 | Interrupt Clear Register | | |
ab_TCR | 0x28 | 32 | Timestamp Control Register | | |
ab_WIR | 0x2c | 32 | Watermark Interrupt Register | | |
ab_TXFIFO_ID | 0x30 | 32 | transmit message fifo message identifier | | |
ab_TXFIFO_DLC | 0x34 | 32 | transmit message fifo data length code | | |
ab_TXFIFO_DATA1 | 0x38 | 32 | transmit message fifo data word 1 | | |
ab_TXFIFO_DATA2 | 0x3c | 32 | transmit message fifo data word 2 | | |
ab_TXHPB_ID | 0x40 | 32 | transmit high priority buffer message identifier | | |
ab_TXHPB_DLC | 0x44 | 32 | transmit high priority buffer data length code | | |
ab_TXHPB_DATA1 | 0x48 | 32 | transmit high priority buffer data word 1 | | |
ab_TXHPB_DATA2 | 0x4c | 32 | transmit high priority buffer data word 2 | | |
ab_RXFIFO_ID | 0x50 | 32 | receive message fifo message identifier | | |
ab_RXFIFO_DLC | 0x54 | 32 | receive message fifo data length code | | |
ab_RXFIFO_DATA1 | 0x58 | 32 | receive message fifo data word 1 | | |
ab_RXFIFO_DATA2 | 0x5c | 32 | receive message fifo data word 2 | | |
ab_AFR | 0x60 | 32 | Acceptance Filter Register | | |
ab_AFMR1 | 0x64 | 32 | Acceptance Filter Mask Register 1 | | |
ab_AFIR1 | 0x68 | 32 | Acceptance Filter ID Register 1 | | |
ab_AFMR2 | 0x6c | 32 | Acceptance Filter Mask Register 2 | | |
ab_AFIR2 | 0x70 | 32 | Acceptance Filter ID Register 2 | | |
ab_AFMR3 | 0x74 | 32 | Acceptance Filter Mask Register 3 | | |
ab_AFIR3 | 0x78 | 32 | Acceptance Filter ID Register 3 | | |
ab_AFMR4 | 0x7c | 32 | Acceptance Filter Mask Register 4 | | |
ab_AFIR4 | 0x80 | 32 | Acceptance Filter ID Register 4 | | |
Platforms that use this peripheral component
Peripheral components can be used in many different platforms, including those developed by Imperas or by other users of OVP. You can use this peripheral in your own platforms.
Table 3: Publicly available platforms using peripheral 'zynq_7000-can'