OVP Peripheral Model: XilinxZynq7000Qos301

Model Specific Information

This page provides introductory usage information for an Imperas OVP peripheral behavioral model. The page is split into sections providing specific information for this peripheral, including any ports for connecting into a platform, registers, other component parts, and configuration options and general information for peripheral modeling with Imperas OVP.


Zynq 7000 Platform Interconnect QoS (qos301)


Open Source Apache 2.0


This model implements the full set of registers. There is no behavior included.


Zynq-7000 TRM (


The zynq_7000-qos301 peripheral model is located in an Imperas/OVP installation at the VLNV: / peripheral / zynq_7000-qos301 / 1.0.

Bus Slave Ports

This model has the following bus slave ports:

Bus Slave Port: bport1

Table : Bus Slave Port: bport1

NameSize (bytes)Must Be ConnectedDescription
bport10x1000T (True)

Table 1: Bus Slave Port: bport1 Registers:

NameOffsetWidth (bits)DescriptionR/Wis Volatile
ab_qos_cntl0x10c32The QoS control register contains the enable bits for all the regulators.
ab_max_ot0x11032Maximum number of outstanding transactions
ab_max_comb_ot0x11432Maximum number of combined outstanding transactions
ab_aw_p0x11832AW channel peak rate
ab_aw_b0x11c32AW channel burstiness allowance
ab_aw_r0x12032AW channel average rate
ab_ar_p0x12432AR channel peak rate
ab_ar_b0x12832AR channel burstiness allowance
ab_ar_r0x12c32AR channel average rate

Platforms that use this peripheral component

Peripheral components can be used in many different platforms, including those developed by Imperas or by other users of OVP. You can use this peripheral in your own platforms.

Table 2: Publicly available platforms using peripheral 'zynq_7000-qos301'

Platform NameVendor

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