OVP Peripheral Model: XilinxZynq7000Swdt

Model Specific Information

This page provides introductory usage information for an Imperas OVP peripheral behavioral model. The page is split into sections providing specific information for this peripheral, including any ports for connecting into a platform, registers, other component parts, and configuration options and general information for peripheral modeling with Imperas OVP.


Zynq 7000 System Watchdog Timer Registers


Open Source Apache 2.0


This model implements the full set of registers but no behavior.


Zynq-7000 TRM (


The zynq_7000-swdt peripheral model is located in an Imperas/OVP installation at the VLNV: / peripheral / zynq_7000-swdt / 1.0.

Peripheral Instance Parameters

This model accepts the following parameters:

Table : Peripheral Parameters

pclkdoubleWatchdog PCLK Clock Rate in MHz (default 100 MHz)

Net Ports

This model has the following net ports:

Table 1: Net Ports

NameTypeMust Be ConnectedDescription
wdooutputF (False)Watchdog interrupt output signal
rstoutputF (False)Watchdog reset output signal

Bus Slave Ports

This model has the following bus slave ports:

Bus Slave Port: bport1

Table 2: Bus Slave Port: bport1

NameSize (bytes)Must Be ConnectedDescription
bport10x1000T (True)

Table 3: Bus Slave Port: bport1 Registers:

NameOffsetWidth (bits)DescriptionR/Wis Volatile
ab_MODE0x032WD zero mode register
ab_CONTROL0x432Counter Control Register
ab_RESTART0x832Restart key register - this not a real register as no data is stored
ab_STATUS0xc32Status Register

Platforms that use this peripheral component

Peripheral components can be used in many different platforms, including those developed by Imperas or by other users of OVP. You can use this peripheral in your own platforms.

Table 4: Publicly available platforms using peripheral 'zynq_7000-swdt'

Platform NameVendor

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